Debug & Test Ports (DTP)

The Debug & Test Ports (DTP) module provides debug and test infrastructure. It integrates the JTAG Interface Unit (JIU) and the Cross Trigger Network (CTN) into a single instantiable subsystem that exposes a standard external JTAG port, internal debug bridges, and a configurable cross-trigger fabric.

DTP (uvm, vcs) verification status DTP (uvm, vcs) test pass rate DTP (uvm, vcs) coverage

1. Capabilities

  • JTAG access — IEEE 1149.1-2013 Primary TAP with configurable Secondary TAPs for hierarchical multi-chiplet debug connectivity per IEEE 1838-2019 (3DIC).

  • iJTAG chains — IEEE 1687-2014 SIB-based chains for DFT secure, DFT non-secure, and DFD instrumentation, plus SMC and SEP OTP debug bridges.

  • JTAG2AXI bridges — SMC fabric, SMC OTP and SEP OTP debug access without system software.

  • Cross-trigger fabric — Configurable network (1–32 external CTPs, 0–32 internal cross triggers) supporting both wire-OR and point-to-point signalling per the Open Chiplet Cross Triggering (OCCT) specification.

  • Clock stop — Unified halt path combining JTAG DEBUG_CONTROL and CLA clock-stop requests, with separate CLA-only readback for software observation.

  • Lifecycle feature control — SEP-driven enable polarity gates eleven debug and test paths (five STAP/scan paths, three iJTAG chains and three JTAG2AXI bridges) independently.

2. Reading Order