Interconnect

Figure 1 shows the crossbar connectivity implemented in hw/sys/sep/rtl/crossbars/sep_local_axi_xbar.sv, along with the dedicated Boot ROM path that lies outside the crossbar. The crossbar has five initiators (CPU IFU, CPU LSU, CPU DBG, DMA, and the System Interface) and ten targets. The CPU masters and the DMA issue single-beat transactions only; the System Interface may issue bursts.

A few access paths are intentionally outside this crossbar:

The System Periph target aggregates the System Bus interface, the dual scratch register bank, the AP/STEE remap regions, and the outbound routing to SMC/SMN resources.

The Entropy Pool target is sep_entropy_fifo (0x1095_0000): a 64-bit read-only entropy drain aperture, filled autonomously by a native EDN endpoint on a separate hardware path (not this crossbar). Writes to it terminate with BRESP=SLVERR.

The SRAM target serves INCR bursts of every length and single-beat bursts of every type. A multi-beat FIXED or WRAP burst is refused before it reaches the memory: the write terminates with BRESP=SLVERR and leaves SRAM unchanged, and every beat of the read returns RRESP=SLVERR.

The System Interface initiator is the external inbound master. It does not attach to this crossbar directly; it enters SEP through the dedicated smn_inbound port and the inbound traffic filter (block-by-default), then through the sep_system_peripherals inner crossbar. That inner crossbar reaches the mailboxes and system CSRs directly, and loops everything else back into this crossbar’s System Interface initiator. The inbound filter controls which addresses the external master may reach; it is block-by-default after POR and configured by SEP firmware.

The input fabric admits external traffic through the inbound filter and system-peripheral decode. The local fabric connects SEP initiators to local resources, while the output fabric selects remapped or direct outbound paths.

In the fabric diagrams, labels such as ID 3 to 4 give the input and output AXI transaction-ID widths in bits; they do not count ports or data bits. The wider side of the symbol indicates the side with multiple ports. Bus labels identify address and ID widths where they change. The filter wrapper checks reads and writes independently, forwards permitted requests, and routes rejected requests to an AXI error responder.

The input paths are shown in Figure 2, the local resource connections in Figure 3, and the outbound paths in Figure 4. The three figures share one notation. Crossbars are rectangles, muxes and demuxes are trapezoids with the wide side towards the many ports, address remaps are hexagons and traffic filters are octagons. Green boxes are converters: address-width, data-width, ID-width and protocol conversion, and register cuts. Thick lines are AXI4 and thin lines AXI-Lite or TL-UL; every AXI data path is 64 bits wide unless a converter narrows it. The labels give the address and ID widths where they change, and the port badges mark where a path crosses the module boundary.

Figure 2 follows a request from the system interconnect through sep_system_peripherals. The inbound filter checks it first; while SEP-scope debug is enabled, SEP_DBG bypasses the filter. The global-to-local remap then rebases the SEP_REGION_SIZE window at SEP_GLOBAL_BASE_ADDR to address 0 and passes every other address unchanged. The peripheral crossbar has a second initiator, the SEP_LOCAL port of the output fabric’s route demux, so local masters reach the mailboxes and system CSRs through the same decode. Addresses outside the mailbox and system CSR windows but below 0x4000_0000 are truncated to 32 bits, their IDs reduced from 7 to 3 bits, and forwarded to the ext initiator of the local crossbar. Inside the system CSR windows the crossbar decodes each register block separately and answers the addresses between them with DECERR on reads and writes, as it does any address at or above 0x4000_0000. The system CSRs program the inbound filter entries and the SEP aperture, as well as the output fabric’s remaps and outbound filter.

Figure 3 shows the local crossbar with its initiators on the left and its targets on the right, in crossbar port order. Each CPU master and the secure DMA master pass a local alias remap before the crossbar; the remap rewrites the 768 MiB window at SEP_LOCAL_BASE_ADDR to 0x1000_0000. The IFU and LSU demuxes inside sep_cpu send boot ROM addresses to the boot ROM mux, which reaches the ROM macro without passing the crossbar, and the IFU demux answers addresses outside the boot ROM and SEP SRAM with DECERR. The chain on each target row is the conversion the target needs: the secure DMA registers and the watchdog are reached as 32-bit TL-UL, and the IO block, reset controller and entropy pool as AXI-Lite. The sep_external demux diverts the eFuse shim CSR window to the eFuse wrapper; every other address in the 0x2000_0000 to 0x3FFF_FFFF aperture leaves SEP on the AXI extension port. Figure 1 gives the initiator-to-target connections.

Figure 4 follows local-master traffic that the local crossbar sends to sep_system_peripherals. The address is zero-extended from 32 to 56 bits, passes the 16-region alias remap and a register cut, and reaches the route demux. The demux takes the first match in the order shown: the SMC aperture, supplied by the SMC, goes straight to the SMC without filtering; the SMU aperture from SMU_GLOBAL_BASE_ADDR and SMU_REGION_SIZE, and any address at or above 0x1_0000_0000, goes to the outbound mux; the AP and STEE regions pass their output remaps, which replace the address with the programmed region offset and set the source ID to OTHERS, before the same mux; and every other address returns to the peripheral crossbar of the input fabric. The outbound mux widens the ID from 6 to 8 bits, and the outbound filter, which has no bypass, guards the path to the system interconnect.

Local SEP resources include peripheral CSRs, SRAM and the AP- and STEE-controlled remappers. SEP CPU direct addresses, the CPU local-alias view and the external global aperture are distinct views, as described in Address Remapping.

Neighboring SMC resources are accessed through the SMC global aperture programmed by SMC firmware and supplied to SEP/SMU integration logic. That aperture is independent from the SEP CPU local-alias range.

Traffic not routed to local SEP or neighboring SMC resources goes to the SMN system NoC, either through the AP- or STEE-controlled remappers, which external software such as the Ascalon AP controls, or through the direct SMN path.

SEP outbound traffic carries a source ID in AxUSER. Both AP- and STEE-controlled remappers replace it with OTHERS. Other traffic retains the initiator’s ID: the CPU masters drive SEP’s ID, while the secure DMA master leaves AxUSER at zero (OTHERS). AxPROT, including NS, passes unchanged; the initiators' values are in [sep-cpu-axprot-table]. The outbound filter checks address, NS and source ID after remapping. The Programmer’s Guide describes how to select the outbound path and restrict OTHERS traffic.

The inbound filter blocks traffic by default. Its entries reside in the system CSRs, reached directly by local masters and by external masters only through an enabled inbound filter entry (or the stated SEP debug bypass). Matching rules are in Filtering and Protection.

See Mailboxes under Peripherals for host mailbox operation.

See Mailbox architecture and interrupt routing.

See Mailbox qualification.

The Memory Map chapter lists the address windows. The common AXI Traffic Filter reference describes the filter register layout and programming rules.

Memory Map; AXI Traffic Filter.

See the owning register references linked above.