Clocks and Resets

1. Clock Domains

The DTP operates in two clock domains (Table 1).

Table 1. DTP clock domains
Domain	Signal	Description
System clock	`clk_i`	Main clock for cross-trigger logic and AXI interfaces. All CTN and CSR logic runs in this domain.
JTAG clock	TCK	JTAG test clock for all TAP controller and scan logic. Clocks the PTAP, STAP state machines, and scan registers. Asynchronous to `clk_i`.

The combined JTAG and CLA clock-stop request crosses into clk_i through two synchronizer stages in ctn_clock_stop_ctrl, followed by an output register. The CLA clock-stop status also crosses into TCK through the DEBUG_CONTROL TDR’s two-flop u_cla_clock_stop_sync synchronizer before bit 4 captures it. The CTP handshake crossings are described in the port reference.

2. Reset Architecture

Table 2 identifies the reset inputs and the logic they reset.

Table 2. DTP reset signals
Signal	Description
`rst_n_i`	Active-low asynchronous reset for cross-trigger logic and AXI interfaces. Resets all CTN and CSR state; clock-stop output resets to 0 (clocks running).
`pwr_on_rst_ni`	Active-low asynchronous power-on reset for JTAG logic. Combined internally with TRST_n; resets the PTAP to Test-Logic-Reset state and clears all TDRs.
TRST_n (JTAG pin)	Optional external active-low TAP reset. When asserted, drives the PTAP to Test-Logic-Reset regardless of the TCK or TMS state.

All registers reset to safe states. The JTAG TAP returns to Test-Logic-Reset on either TRST_n or power-on reset.

3. IC_RESET Overrides

The primary TAP exposes a reset-selection test data register (TDR) through IC_RESET. IEEE 1149.1-2013 defines the instruction in Clause 8.21 and the reset-selection register in Clause 17. The IEEE working-group summary of the 2013 changes identifies both clauses. In this implementation, per reset port it holds reset_control, the active-low reset value to drive, and reset_enable, which selects it. One reset_hold bit sits nearest TDO.

reset_enable is active low despite the name: it resets to 1, leaving the port’s functional reset connected, and writing 0 hands the port over to reset_control. The overrides leave the DTP on jtag_ic_reset_{smc,sep,ext}_o, whose .ovrd member is active high and whose .val carries reset_control.

reset_hold also resets to 1, which lets Test-Logic-Reset clear the enable/control bits. Write 0 to keep an override asserted across TLR; only TRST clears reset_hold itself.

Consumers select between the two sources with a hazard-free multiplexer, which holds its output while the select alone moves. Moving reset_enable and reset_control in one Update-DR changes the select and a data input together, which can pulse a reset on a port that neither source is resetting. The Programmer’s Guide gives the override sequence.

At the SMU the TDR concatenates three slices from TDI to TDO: SMC, SEP, then the external slice, followed by reset_hold. The SMC and SEP port lists are OCAH-defined. The external slice is adopter-defined: its width and fields come from the SMU type parameter ic_reset_ext_t. The Integrator Guide records the SMU-composed port map.

4. Clock Stop

The DTP combines JTAG DEBUG_CONTROL and CLA clock-stop request sources into one functional chiplet halt path, while keeping the CLA-only status separate for debugger readback.

4.1. Halt Path Architecture

Figure 1 shows how JTAG and CLA requests contribute to the chiplet halt path, with the DTP as the SMU instantiates it. The DEBUG_CONTROL TDR is drawn as its five bits, with bit 0 nearest TDO. The grey box below the DTP is the part of the SMC DFD block (smc_dfd_wrap) that produces the SMC’s clock-stop request and exchanges cross-triggers with the DTP. Gate and flop symbols draw the logic of the path, and CDC badges mark the two-flop synchronizers where a signal enters the TCK or clk_i domain.

Figure 1. DTP JTAG and CLA clock-stop aggregation

Three distinct signals participate in clock stop:

jtag_clock_stop (JTAG DEBUG_CONTROL bit 3): Written through the DEBUG_CONTROL TDR (IR 0x18) in the primary TAP and routed to the CTN clock-stop controller. OR-combined with CLA requests to form the registered stop_clks_o output that connects to chiplet functional clock gating. The bit resets on TRST, on power-on reset and whenever the TAP enters Test-Logic-Reset.
cla_clock_stop_en (JTAG DEBUG_CONTROL bit 2): Exported at the DTP top level as cla_clock_stop_en_o. It is not part of the stop_clks_o aggregation inside the CTN. In the SMU it drives the SMC DFD’s tdr_dbg_ctrl_clock_stop_en_i, which gates the SMC CLA’s clock-stop request on xtrig_clk_stop_req_i[0], so it decides whether the SMC CLA can halt the chiplet.
CLA clock-stop indication: The CTN OR-reduces xtrig_clk_stop_req_i (CLA sources only, not jtag_clock_stop) to form the cla_clock_stop readback status. The OR is combinational, so the DEBUG_CONTROL TDR passes it through a two-flop TCK synchronizer before bit 4 captures it in Capture-DR. A debugger reads it there to observe whether any CLA clock-stop source is active.

4.2. Signal Flow

The JTAG Interface Unit captures DEBUG_CONTROL bits in the TCK domain. The jtag_clock_stop bit is routed to the CTN clock-stop controller; cla_clock_stop_en is exported at the DTP boundary.
The CTN OR-reduces xtrig_clk_stop_req_i to produce cla_clock_stop status, then OR-combines that aggregate with jtag_clock_stop. The result passes a two-flop clk_i synchronizer and an output flop to produce stop_clks_o, which follows the requests three clk_i cycles later and is low while rst_n_i is asserted.
The cla_clock_stop status is fed back into the DEBUG_CONTROL readback path so a debugger can observe CLA clock-stop source activity independently of its own direct-stop assertion.

This architecture keeps CLA observability distinct from the JTAG direct-stop path, while either source can assert the functional chiplet halt through stop_clks_o.

In the SMU, lane 0 of the XTRIG_NUM_CLK_STOP_REQ xtrig_clk_stop_req_i lanes carries the SMC DFD’s clocks-stopped output. That output is the CLA halt-clock action, masked by bit 0 of xtrig_clk_halt_mask in the SMC DFX CSRs and ANDed with cla_clock_stop_en_o; it also raises an SMC CPU interrupt. The remaining lanes, xtrig_clk_stop_req_i[XTRIG_NUM_CLK_STOP_REQ-1:1], come from the SMU’s own xtrig_clk_stop_req_i ports. The same mask gates the CLA cross-trigger outputs, which reach the cross-trigger matrix through internal lanes 1 and 0 (xtrig_ctm_dst_req_i[1:0]); xtrig_ctm_src_req_o[1:0] returns to the CLA. The SMU runs both SMC lanes in pulse-synchronization mode and ties their acknowledges low, and exports internal lanes 9 to 2.

For the CTN clock-stop controller implementation and the xtrig_clk_stop_req_i input indexing, see Cross-Trigger Network.

5. Clock Distribution

Figure 2 shows which DTP blocks use the system clock and which use TCK. The DTP has two clocks and no clock gates. clk_i, the system clock (clk_smu_i in the SMU), clocks the whole cross-trigger network and the AXI side of the three JTAG2AXI bridges. TCK, from jtag_ptap_client_tap_ctrl_i.tck, clocks the rest of the JTAG interface unit. Each block is tinted by the clock that runs it, and each clock has one arrow into each hierarchy it reaches. CDC badges mark the blocks that synchronize a signal from another domain: the cross-trigger port input synchronizers, the clock-stop controller, the dbg_disable_i synchronizers, the DEBUG_CONTROL cla_clock_stop synchronizer and the JTAG2AXI bridges' u_axi_cdc. TCK leaves the DTP unchanged on the host TAP control of every STAP and on the host scan control of the boundary-scan, extended STAP, DFT and DFD ports.

Figure 2. DTP system-clock and JTAG-clock distribution

6. Reset Distribution

Figure 3 shows the reset distribution for DTP system logic and the JTAG scan paths. Each reset has its own colour, and the input names below the DTP ports are the SMU nets that drive them. Gate and flop symbols show where resets are combined, and a reset ends on the bottom edge of the flop it resets.

rst_n_i (rst_primary_smc_clk_no in the SMU) resets the cross-trigger network and the AXI side of the JTAG2AXI bridges.
pwr_on_rst_ni (powergood_stable in the SMU) sets the dbg_disable_i synchronizers to 1, disabling every debug path until the lifecycle value arrives. u_trst_n_and ANDs it with the TRST pin to form the combined TRST.
The combined TRST resets the TAP controller, including its Test-Logic-Reset flop, the TMP controller and the TDO retiming flop. It also resets the hold flops of the 3DCR and IC_RESET TDRs, the 3DCR scan register and the STAPs, and leaves unchanged on the host TAP control of every STAP.
The TAP controller derives the scan reset rst_n, which is low in Test-Logic-Reset, and the scan channel reset chrst_n, which the TMP persistence mode holds released through Test-Logic-Reset. rst_n resets the instruction register, most TDRs, the TCK side of the JTAG2AXI bridges, the STAPs and the SIBs. The 3DCR TDR takes it only while its hold bit is clear, and the IC_RESET TDR only while its reset_hold bit is set. chrst_n is not used inside the DTP; both leave on the host scan control of the boundary-scan, extended STAP, DFT and DFD ports.

The two-flop cla_clock_stop synchronizer in the DEBUG_CONTROL TDR has no reset. test_en_i drives the test mode of the cross-trigger network and the JTAG2AXI bridges. scan_rst_ni is not connected inside the DTP, which has no reset synchronizer, so rst_n_i must arrive scan-controlled. A STAP whose enable parameter is 0 drives its host TRST low.

DTP reset distribution: rst_n_i to the cross-trigger network and JTAG2AXI AXI side, power-on reset ANDed with TRST into the TAP controller, which derives the scan resets for the TDRs, STAPs, SIBs and host scan ports

Figure 3. DTP system and JTAG reset distribution