Watchdog Timer (WDT)

The sep_wdt_wrap module integrates the OpenTitan aon_timer IP as the watchdog timer. The 64-bit AXI slave port from the system crossbar is narrowed to 32-bit AXI through an axi_dw_converter. The address path subtracts the WDT base address so that the internal TL-UL decoder sees zero-based offsets. After axi_to_axi_lite and axi_lite_to_tlul conversion, the TL-UL bus drives the standard aon_timer register block.

The wrapper provides a dedicated watchdog clock input (clk_wdt_i) that is synchronized through a prim_sync_reset to produce the rst_aon_ni reset for the always-on timer domain. The wdt_debug_sleep_mode_i input controls whether the timer continues to count during debug halt. Life-cycle escalation is tied to its inactive state. Alert receivers are initialized to the idle encoding to avoid spurious integrity errors; alert outputs are left unconnected since the SEP aggregates watchdog events through the interrupt path.

The wrapper exports two signals: intr_wdog_timer_bark_o, the watchdog bark interrupt that fires when the first timeout stage expires, and wdt_timer_rst_req_o, the bite reset request that fires when the second timeout stage expires and the system failed to respond to the bark.

Consult the OpenTitan Always-On Timer documentation for the authoritative core functionality of the IP. The Programmer’s Guide gives the programming guidance for this block. The register map follows below.