OCAH Architecture & Design

This section provides an overview of the OCAH architecture including its subsystem composition, power and clock domains, reset hierarchy, and memory map. It is organised into focused topic pages; subsequent chapters provide detailed microarchitectural documentation for each subsystem.

1. RTL Assertions

First-party RTL uses the OCAH_ASSERT* macros; OpenTitan-derived blocks use OCAH_OT_ASSERT*; PULP-vendored cells (common_cells, AXI, iDMA) use OCAH_PULP_ASSERT*. The checks live in the module that owns the behavior and cover known-value hygiene, illegal parameter combinations, and local protocol or FSM invariants. They compile out of synthesis and fire on four-state simulators.

Table 1 identifies the header for each assertion macro family.

Table 1. RTL assertion macro families
Family Header

OCAH_ASSERT*

hw/common/assert/ocah_assert.svh

OCAH_OT_ASSERT*

vendor/lowRISC/opentitan/upstream/hw/ip/prim/rtl/prim_assert.sv

OCAH_PULP_ASSERT*

vendor/pulp-platform/common_cells/upstream/include/common_cells/assertions.svh

  • Platform Overview — the high-level features of each OCAH subsystem and the top-level block diagram.

  • OCAH Memory Map — the chiplet-visible SMU aperture and the SEP and SMC global apertures programmed by firmware.

  • Power Domains — the always-on management domain and the isolation and sequencing infrastructure provided for adopter-defined domains.

  • Clock Domains — management versus functional timing, the clock domain table, and the reference counter.

  • Reset — the hierarchical reset model and the SMU reset sequence.