I3C Controller

The I3C controller is based on the CHIPS Alliance i3c-core. Controller and target behavior, the HCI queues, common command codes, and the bus protocol are specified by that design.

CHIPS Alliance i3c-core reference architecture
Figure 1. CHIPS Alliance i3c-core reference architecture

Figure 1 shows the upstream core.

1. OCAH Modifications

When target mode is used, budget four core-clock cycles for the internal SCL-to-SDA response. A 12 ns turnaround limit requires approximately 333.3 MHz or faster before pad and routing allowance; see the Peripheral Timing Requirements section and the upstream PHY timing requirements. Controller-mode timing examples at lower frequencies do not demonstrate compliance with this target-mode limit.

SMC instantiates six controllers. i3ccore_wrapper exposes one AXI4-Lite slave and selects the instance from the address. Instances are spaced by 0x1000, and each instance is presented with a 12-bit offset inside that window.

i3c_wrapper drives the core’s AXI4 register port as a single beat: awlen and arlen are 0 and wlast is 1. The core’s controller-mode SCL and SDA outputs are bus levels. The wrapper turns those into open-drain pad enables: SCL is driven only low, and SDA is driven in both directions while push-pull mode is selected.

Each instance brings out its device-address, device-characteristic, and reverse-lookup memories, one interrupt, and the recovery pins.

i3ccore_wrapper: an AXI-Lite demux in front of NUM_I3C i3c_wrapper instances, each passing a 12-bit offset as single-beat AXI4 to the CHIPS Alliance i3c-core and deriving open-drain pad enables
Figure 2. OCAH I3C wrapper

Figure 2 shows that wrapper around the CHIPS Alliance core, which it draws as a black box. Parentheses after an instance name give its module or, for a block taken from another project, that project; the demux is a PULP axi_lite_demux. i3ccore_wrapper runs on one clock, clk_i; in the SMC that is the gated peripheral clock, and its AXI4-Lite port, with 32-bit address and data, arrives through smc_peripherals_cdc. The demux u_axil_demux registers every channel and allows eight outstanding transactions. It has no error slave: an address outside every instance window reaches instance 0. Each generate block subtracts its index times 0x1000 from the address before i3c_wrapper sees it.

Inside i3c_wrapper, the converter tie-offs are awlen/arlen 0, wlast 1, and zero ID and user. The gates below the core are the pad-enable logic: scl_o is tied low and scl_oe_o is the inverse of the core’s SCL level, so the pad only pulls SCL low; sda_o is the core’s SDA level and sda_oe_o is sel_od_pp_o OR the inverse of sda_o. The core’s own SDA output enable, which it drives only in target mode, is not used.

irq_o, the five recovery signals and the DAT, DCT and reverse-lookup memory ports pass straight through to per-instance vectors on the i3ccore_wrapper boundary. In the SMC recovery_payload_available_o, recovery_image_activated_o, peripheral_reset_o and escalated_reset_o are left unconnected, peripheral_reset_done_i is tied low, and the interrupts reach peripheral interrupts 12 to 17.

The register map below reproduces the upstream SystemRDL descriptions; those under I3C_EC are upstream’s own rather than MIPI I3C HCI text. The fields below differ from or go beyond those descriptions.

These read back the value written but reach no logic:

  • PIOControl.PIO_CONTROL.ENABLE: the PIO queues are always enabled.

  • I3C_EC.StdbyCtrlMode.STBY_CR_CONTROL.TARGET_XACT_ENABLE: target transactions cannot be disabled.

  • I3C_EC.StdbyCtrlMode.STBY_CR_CONTROL.RSTACT_DEFBYTE_02: RSTACT with defining byte 0x02 is always ACKed.

  • I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS.RESET_TIME_PERIPHERAL and RESET_TIME_TARGET: GET RSTACT with defining byte 0x81 or 0x82 returns 0xFF.

  • I3C_EC.SoCMgmtIf.REC_INTF_CFG.REC_INTF_BYPASS: DISABLE_LOOPBACK ties the bypass off, so recovery always goes through the I3C core.

These misreport the core:

  • I3C_EC.StdbyCtrlMode.STBY_CR_CAPABILITIES.DAA_ENTDAA_SUPPORT reads 0, but ENTDAA is supported.

  • I3C_EC.StdbyCtrlMode.STBY_CR_CONTROL.STBY_CR_ENABLE_INIT mode 2’b11 behaves as 2’b01 (active controller), not Hot-Join-then-standby.

These behave as follows, which the descriptions leave unstated:

  • I3C_EC.TTI.TARGET_ERR_CNT_TE3 counts parity errors on the ENTDAA-assigned dynamic address; TARGET_ERR_CNT_TE4 counts reserved bytes other than 7’h7E with R/W=1.

  • I3C_EC.TTI.TARGET_ERR_CNT_RI_RX_FIFO_OVERFLOW and TARGET_ERR_CNT_RI_INDIRECT_FIFO_OVERFLOW: the enable in TARGET_ERR_CTRL gates detection, so an overflow while it is clear is neither counted nor interrupts.

  • PIOControl.DATA_BUFFER_THLD_CTRL: RX_START_THLD and TX_BUF_THLD test free space, TX_START_THLD and RX_BUF_THLD stored entries; each encodes 2^(N+1) entries.

  • PIOControl.QUEUE_THLD_CTRL: raw entry counts, free for CMD_EMPTY_BUF_THLD and stored for RESP_BUF_THLD and IBI_STATUS_THLD. Only these ready thresholds are implemented; start thresholds are unconnected.

  • DCT.DCT_MEMORY: PID_LO holds the first two (most significant) ENTDAA PID bytes and PID_HI the next four. DYNAMIC_ADDRESS holds the address in bits 7:1 and its odd parity in bit 0.

Consult the i3c-core documentation for the controller. The register map of this wrapper follows.

2. Memory Map and Register Reference

2.1. Memory Map

2.1.1. Integration Limits

The SoC Management Interface header at 0x300 reports CAP_LENGTH = 0x1A DWORDs. This is inconsistent with the next capability header at 0x398: the span is 0x98 bytes, or 0x26 DWORDs. A generic walker that trusts the reported length advances to 0x368, inside the timing registers, and misinterprets data as a capability header. Software for this implementation must use the offsets in this paragraph rather than discovering that boundary from CAP_LENGTH.

The DAT and DCT capability fields advertise TABLE_SIZE = 127, but only 16 independent entries are implemented. Index decoding retains four bits, so higher window slots alias lower entries rather than providing extra storage. For example, DAT slot 16 at 0x480 aliases slot 0 at 0x400; DCT slot 16 at 0x900 aliases slot 0 at 0x800. Limit accesses to indexes 0–15. The complete windows in the generated map describe address decoding, not independent 128-entry capacity.

2.2. Detailed Register Map

OCA I3C Controller Wrapper Address Map

Wrapper address map instantiating the per-controller I3C CSR blocks.

Register Arrays:

  • i3c_csr[6].I3CBase.HCI_VERSION: 6 registers, base 0x0, stride 0x1000
  • i3c_csr[6].I3CBase.HC_CONTROL: 6 registers, base 0x4, stride 0x1000
  • i3c_csr[6].I3CBase.CONTROLLER_DEVICE_ADDR: 6 registers, base 0x8, stride 0x1000
  • i3c_csr[6].I3CBase.HC_CAPABILITIES: 6 registers, base 0xC, stride 0x1000
  • i3c_csr[6].I3CBase.RESET_CONTROL: 6 registers, base 0x10, stride 0x1000
  • i3c_csr[6].I3CBase.PRESENT_STATE: 6 registers, base 0x14, stride 0x1000
  • i3c_csr[6].I3CBase.INTR_STATUS: 6 registers, base 0x20, stride 0x1000
  • i3c_csr[6].I3CBase.INTR_STATUS_ENABLE: 6 registers, base 0x24, stride 0x1000
  • i3c_csr[6].I3CBase.INTR_SIGNAL_ENABLE: 6 registers, base 0x28, stride 0x1000
  • i3c_csr[6].I3CBase.INTR_FORCE: 6 registers, base 0x2C, stride 0x1000
  • i3c_csr[6].I3CBase.DAT_SECTION_OFFSET: 6 registers, base 0x30, stride 0x1000
  • i3c_csr[6].I3CBase.DCT_SECTION_OFFSET: 6 registers, base 0x34, stride 0x1000
  • i3c_csr[6].I3CBase.RING_HEADERS_SECTION_OFFSET: 6 registers, base 0x38, stride 0x1000
  • i3c_csr[6].I3CBase.PIO_SECTION_OFFSET: 6 registers, base 0x3C, stride 0x1000
  • i3c_csr[6].I3CBase.EXT_CAPS_SECTION_OFFSET: 6 registers, base 0x40, stride 0x1000
  • i3c_csr[6].I3CBase.INT_CTRL_CMDS_EN: 6 registers, base 0x4C, stride 0x1000
  • i3c_csr[6].I3CBase.IBI_NOTIFY_CTRL: 6 registers, base 0x58, stride 0x1000
  • i3c_csr[6].I3CBase.IBI_DATA_ABORT_CTRL: 6 registers, base 0x5C, stride 0x1000
  • i3c_csr[6].I3CBase.DEV_CTX_BASE_LO: 6 registers, base 0x60, stride 0x1000
  • i3c_csr[6].I3CBase.DEV_CTX_BASE_HI: 6 registers, base 0x64, stride 0x1000
  • i3c_csr[6].I3CBase.DEV_CTX_SG: 6 registers, base 0x68, stride 0x1000
  • i3c_csr[6].PIOControl.COMMAND_PORT: 6 registers, base 0x80, stride 0x1000
  • i3c_csr[6].PIOControl.RESPONSE_PORT: 6 registers, base 0x84, stride 0x1000
  • i3c_csr[6].PIOControl.TX_DATA_PORT: 6 registers, base 0x88, stride 0x1000
  • i3c_csr[6].PIOControl.RX_DATA_PORT: 6 registers, base 0x88, stride 0x1000
  • i3c_csr[6].PIOControl.IBI_PORT: 6 registers, base 0x8C, stride 0x1000
  • i3c_csr[6].PIOControl.QUEUE_THLD_CTRL: 6 registers, base 0x90, stride 0x1000
  • i3c_csr[6].PIOControl.DATA_BUFFER_THLD_CTRL: 6 registers, base 0x94, stride 0x1000
  • i3c_csr[6].PIOControl.QUEUE_SIZE: 6 registers, base 0x98, stride 0x1000
  • i3c_csr[6].PIOControl.ALT_QUEUE_SIZE: 6 registers, base 0x9C, stride 0x1000
  • i3c_csr[6].PIOControl.PIO_INTR_STATUS: 6 registers, base 0xA0, stride 0x1000
  • i3c_csr[6].PIOControl.PIO_INTR_STATUS_ENABLE: 6 registers, base 0xA4, stride 0x1000
  • i3c_csr[6].PIOControl.PIO_INTR_SIGNAL_ENABLE: 6 registers, base 0xA8, stride 0x1000
  • i3c_csr[6].PIOControl.PIO_INTR_FORCE: 6 registers, base 0xAC, stride 0x1000
  • i3c_csr[6].PIOControl.PIO_CONTROL: 6 registers, base 0xB0, stride 0x1000
  • i3c_csr[6].I3C_EC.SecFwRecoveryIf.EXTCAP_HEADER: 6 registers, base 0x100, stride 0x1000
  • i3c_csr[6].I3C_EC.SecFwRecoveryIf.PROT_CAP_0: 6 registers, base 0x104, stride 0x1000
  • i3c_csr[6].I3C_EC.SecFwRecoveryIf.PROT_CAP_1: 6 registers, base 0x108, stride 0x1000
  • i3c_csr[6].I3C_EC.SecFwRecoveryIf.PROT_CAP_2: 6 registers, base 0x10C, stride 0x1000
  • i3c_csr[6].I3C_EC.SecFwRecoveryIf.PROT_CAP_3: 6 registers, base 0x110, stride 0x1000
  • i3c_csr[6].I3C_EC.SecFwRecoveryIf.DEVICE_ID_0: 6 registers, base 0x114, stride 0x1000
  • i3c_csr[6].I3C_EC.SecFwRecoveryIf.DEVICE_ID_1: 6 registers, base 0x118, stride 0x1000
  • i3c_csr[6].I3C_EC.SecFwRecoveryIf.DEVICE_ID_2: 6 registers, base 0x11C, stride 0x1000
  • i3c_csr[6].I3C_EC.SecFwRecoveryIf.DEVICE_ID_3: 6 registers, base 0x120, stride 0x1000
  • i3c_csr[6].I3C_EC.SecFwRecoveryIf.DEVICE_ID_4: 6 registers, base 0x124, stride 0x1000
  • i3c_csr[6].I3C_EC.SecFwRecoveryIf.DEVICE_ID_5: 6 registers, base 0x128, stride 0x1000
  • i3c_csr[6].I3C_EC.SecFwRecoveryIf.DEVICE_ID_RESERVED: 6 registers, base 0x12C, stride 0x1000
  • i3c_csr[6].I3C_EC.SecFwRecoveryIf.DEVICE_STATUS_0: 6 registers, base 0x130, stride 0x1000
  • i3c_csr[6].I3C_EC.SecFwRecoveryIf.DEVICE_STATUS_1: 6 registers, base 0x134, stride 0x1000
  • i3c_csr[6].I3C_EC.SecFwRecoveryIf.DEVICE_RESET: 6 registers, base 0x138, stride 0x1000
  • i3c_csr[6].I3C_EC.SecFwRecoveryIf.RECOVERY_CTRL: 6 registers, base 0x13C, stride 0x1000
  • i3c_csr[6].I3C_EC.SecFwRecoveryIf.RECOVERY_STATUS: 6 registers, base 0x140, stride 0x1000
  • i3c_csr[6].I3C_EC.SecFwRecoveryIf.HW_STATUS: 6 registers, base 0x144, stride 0x1000
  • i3c_csr[6].I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_CTRL_0: 6 registers, base 0x148, stride 0x1000
  • i3c_csr[6].I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_CTRL_1: 6 registers, base 0x14C, stride 0x1000
  • i3c_csr[6].I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_STATUS_0: 6 registers, base 0x150, stride 0x1000
  • i3c_csr[6].I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_STATUS_1: 6 registers, base 0x154, stride 0x1000
  • i3c_csr[6].I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_STATUS_2: 6 registers, base 0x158, stride 0x1000
  • i3c_csr[6].I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_STATUS_3: 6 registers, base 0x15C, stride 0x1000
  • i3c_csr[6].I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_STATUS_4: 6 registers, base 0x160, stride 0x1000
  • i3c_csr[6].I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_RESERVED: 6 registers, base 0x164, stride 0x1000
  • i3c_csr[6].I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_DATA: 6 registers, base 0x168, stride 0x1000
  • i3c_csr[6].I3C_EC.StdbyCtrlMode.EXTCAP_HEADER: 6 registers, base 0x180, stride 0x1000
  • i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_CONTROL: 6 registers, base 0x184, stride 0x1000
  • i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_DEVICE_ADDR: 6 registers, base 0x188, stride 0x1000
  • i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_CAPABILITIES: 6 registers, base 0x18C, stride 0x1000
  • i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_VIRTUAL_DEVICE_CHAR: 6 registers, base 0x190, stride 0x1000
  • i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_STATUS: 6 registers, base 0x194, stride 0x1000
  • i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_DEVICE_CHAR: 6 registers, base 0x198, stride 0x1000
  • i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_DEVICE_PID_LO: 6 registers, base 0x19C, stride 0x1000
  • i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_INTR_STATUS: 6 registers, base 0x1A0, stride 0x1000
  • i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_VIRTUAL_DEVICE_PID_LO: 6 registers, base 0x1A4, stride 0x1000
  • i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_INTR_SIGNAL_ENABLE: 6 registers, base 0x1A8, stride 0x1000
  • i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_INTR_FORCE: 6 registers, base 0x1AC, stride 0x1000
  • i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_GETCAPS: 6 registers, base 0x1B0, stride 0x1000
  • i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS: 6 registers, base 0x1B4, stride 0x1000
  • i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_VIRT_DEVICE_ADDR: 6 registers, base 0x1B8, stride 0x1000
  • i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_MWL: 6 registers, base 0x1BC, stride 0x1000
  • i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_MRL: 6 registers, base 0x1C0, stride 0x1000
  • i3c_csr[6].I3C_EC.TTI.EXTCAP_HEADER: 6 registers, base 0x200, stride 0x1000
  • i3c_csr[6].I3C_EC.TTI.CONTROL: 6 registers, base 0x204, stride 0x1000
  • i3c_csr[6].I3C_EC.TTI.STATUS: 6 registers, base 0x208, stride 0x1000
  • i3c_csr[6].I3C_EC.TTI.RESET_CONTROL: 6 registers, base 0x20C, stride 0x1000
  • i3c_csr[6].I3C_EC.TTI.QUEUE_STATUS: 6 registers, base 0x210, stride 0x1000
  • i3c_csr[6].I3C_EC.TTI.DESC_QUEUE_DEPTH: 6 registers, base 0x214, stride 0x1000
  • i3c_csr[6].I3C_EC.TTI.DATA_QUEUE_DEPTH: 6 registers, base 0x218, stride 0x1000
  • i3c_csr[6].I3C_EC.TTI.IBI_QUEUE_DEPTH: 6 registers, base 0x21C, stride 0x1000
  • i3c_csr[6].I3C_EC.TTI.INTERRUPT_STATUS: 6 registers, base 0x220, stride 0x1000
  • i3c_csr[6].I3C_EC.TTI.INTERRUPT_ENABLE: 6 registers, base 0x224, stride 0x1000
  • i3c_csr[6].I3C_EC.TTI.INTERRUPT_FORCE: 6 registers, base 0x228, stride 0x1000
  • i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CTRL: 6 registers, base 0x22C, stride 0x1000
  • i3c_csr[6].I3C_EC.TTI.TARGET_ERR_INTR_STATUS: 6 registers, base 0x230, stride 0x1000
  • i3c_csr[6].I3C_EC.TTI.TARGET_ERR_INTR_ENABLE: 6 registers, base 0x234, stride 0x1000
  • i3c_csr[6].I3C_EC.TTI.TARGET_ERR_INTR_FORCE: 6 registers, base 0x238, stride 0x1000
  • i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_TE0: 6 registers, base 0x23C, stride 0x1000
  • i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_TE1: 6 registers, base 0x240, stride 0x1000
  • i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_TE2: 6 registers, base 0x244, stride 0x1000
  • i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_TE3: 6 registers, base 0x248, stride 0x1000
  • i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_TE4: 6 registers, base 0x24C, stride 0x1000
  • i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_TE5: 6 registers, base 0x250, stride 0x1000
  • i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_FRAMING: 6 registers, base 0x254, stride 0x1000
  • i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_RI_PEC: 6 registers, base 0x258, stride 0x1000
  • i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_RI_LENGTH: 6 registers, base 0x25C, stride 0x1000
  • i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_RI_READONLY: 6 registers, base 0x260, stride 0x1000
  • i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_RI_UNSUPPORTED: 6 registers, base 0x264, stride 0x1000
  • i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_RI_RX_FIFO_OVERFLOW: 6 registers, base 0x268, stride 0x1000
  • i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_RI_INDIRECT_FIFO_OVERFLOW: 6 registers, base 0x26C, stride 0x1000
  • i3c_csr[6].I3C_EC.TTI.RX_DESC_QUEUE_PORT: 6 registers, base 0x270, stride 0x1000
  • i3c_csr[6].I3C_EC.TTI.RX_DATA_PORT: 6 registers, base 0x274, stride 0x1000
  • i3c_csr[6].I3C_EC.TTI.TX_DESC_QUEUE_PORT: 6 registers, base 0x278, stride 0x1000
  • i3c_csr[6].I3C_EC.TTI.TX_DATA_PORT: 6 registers, base 0x27C, stride 0x1000
  • i3c_csr[6].I3C_EC.TTI.IBI_PORT: 6 registers, base 0x280, stride 0x1000
  • i3c_csr[6].I3C_EC.TTI.QUEUE_SIZE: 6 registers, base 0x284, stride 0x1000
  • i3c_csr[6].I3C_EC.TTI.IBI_QUEUE_SIZE: 6 registers, base 0x288, stride 0x1000
  • i3c_csr[6].I3C_EC.TTI.QUEUE_THLD_CTRL: 6 registers, base 0x28C, stride 0x1000
  • i3c_csr[6].I3C_EC.TTI.DATA_BUFFER_THLD_CTRL: 6 registers, base 0x290, stride 0x1000
  • i3c_csr[6].I3C_EC.SoCMgmtIf.EXTCAP_HEADER: 6 registers, base 0x300, stride 0x1000
  • i3c_csr[6].I3C_EC.SoCMgmtIf.SOC_MGMT_CONTROL: 6 registers, base 0x304, stride 0x1000
  • i3c_csr[6].I3C_EC.SoCMgmtIf.SOC_MGMT_STATUS: 6 registers, base 0x308, stride 0x1000
  • i3c_csr[6].I3C_EC.SoCMgmtIf.REC_INTF_CFG: 6 registers, base 0x30C, stride 0x1000
  • i3c_csr[6].I3C_EC.SoCMgmtIf.REC_INTF_REG_W1C_ACCESS: 6 registers, base 0x310, stride 0x1000
  • i3c_csr[6].I3C_EC.SoCMgmtIf.SOC_MGMT_RSVD_2: 6 registers, base 0x314, stride 0x1000
  • i3c_csr[6].I3C_EC.SoCMgmtIf.SOC_MGMT_RSVD_3: 6 registers, base 0x318, stride 0x1000
  • i3c_csr[6].I3C_EC.SoCMgmtIf.SOC_PAD_CONF: 6 registers, base 0x31C, stride 0x1000
  • i3c_csr[6].I3C_EC.SoCMgmtIf.SOC_PAD_ATTR: 6 registers, base 0x320, stride 0x1000
  • i3c_csr[6].I3C_EC.SoCMgmtIf.SOC_MGMT_FEATURE_2: 6 registers, base 0x324, stride 0x1000
  • i3c_csr[6].I3C_EC.SoCMgmtIf.SOC_MGMT_FEATURE_3: 6 registers, base 0x328, stride 0x1000
  • i3c_csr[6].I3C_EC.SoCMgmtIf.T_R_REG: 6 registers, base 0x32C, stride 0x1000
  • i3c_csr[6].I3C_EC.SoCMgmtIf.T_F_REG: 6 registers, base 0x330, stride 0x1000
  • i3c_csr[6].I3C_EC.SoCMgmtIf.T_SU_DAT_REG: 6 registers, base 0x334, stride 0x1000
  • i3c_csr[6].I3C_EC.SoCMgmtIf.T_SU_DAT_I2C_REG: 6 registers, base 0x338, stride 0x1000
  • i3c_csr[6].I3C_EC.SoCMgmtIf.T_HD_DAT_REG: 6 registers, base 0x33C, stride 0x1000
  • i3c_csr[6].I3C_EC.SoCMgmtIf.T_HIGH_REG: 6 registers, base 0x340, stride 0x1000
  • i3c_csr[6].I3C_EC.SoCMgmtIf.T_HIGH_OD_REG: 6 registers, base 0x344, stride 0x1000
  • i3c_csr[6].I3C_EC.SoCMgmtIf.T_HIGH_INIT_OD_REG: 6 registers, base 0x348, stride 0x1000
  • i3c_csr[6].I3C_EC.SoCMgmtIf.T_HIGH_I2C_REG: 6 registers, base 0x34C, stride 0x1000
  • i3c_csr[6].I3C_EC.SoCMgmtIf.T_LOW_REG: 6 registers, base 0x350, stride 0x1000
  • i3c_csr[6].I3C_EC.SoCMgmtIf.T_LOW_OD_REG: 6 registers, base 0x354, stride 0x1000
  • i3c_csr[6].I3C_EC.SoCMgmtIf.T_LOW_I2C_REG: 6 registers, base 0x358, stride 0x1000
  • i3c_csr[6].I3C_EC.SoCMgmtIf.T_HD_STA_REG: 6 registers, base 0x35C, stride 0x1000
  • i3c_csr[6].I3C_EC.SoCMgmtIf.T_HD_STA_I2C_REG: 6 registers, base 0x360, stride 0x1000
  • i3c_csr[6].I3C_EC.SoCMgmtIf.T_HD_RSTA_REG: 6 registers, base 0x364, stride 0x1000
  • i3c_csr[6].I3C_EC.SoCMgmtIf.T_SU_STA_REG: 6 registers, base 0x368, stride 0x1000
  • i3c_csr[6].I3C_EC.SoCMgmtIf.T_SU_STA_I2C_REG: 6 registers, base 0x36C, stride 0x1000
  • i3c_csr[6].I3C_EC.SoCMgmtIf.T_SU_STO_REG: 6 registers, base 0x370, stride 0x1000
  • i3c_csr[6].I3C_EC.SoCMgmtIf.T_SU_STO_I2C_REG: 6 registers, base 0x374, stride 0x1000
  • i3c_csr[6].I3C_EC.SoCMgmtIf.T_DS_OD_REG: 6 registers, base 0x378, stride 0x1000
  • i3c_csr[6].I3C_EC.SoCMgmtIf.T_FREE_REG: 6 registers, base 0x37C, stride 0x1000
  • i3c_csr[6].I3C_EC.SoCMgmtIf.T_FREE_I2C_REG: 6 registers, base 0x380, stride 0x1000
  • i3c_csr[6].I3C_EC.SoCMgmtIf.T_AVAL_REG: 6 registers, base 0x384, stride 0x1000
  • i3c_csr[6].I3C_EC.SoCMgmtIf.T_IDLE_REG: 6 registers, base 0x388, stride 0x1000
  • i3c_csr[6].I3C_EC.SoCMgmtIf.HDR_TIMEOUT_EN_REG: 6 registers, base 0x38C, stride 0x1000
  • i3c_csr[6].I3C_EC.SoCMgmtIf.T_HDR_TIMEOUT_REG: 6 registers, base 0x390, stride 0x1000
  • i3c_csr[6].I3C_EC.CtrlCfg.EXTCAP_HEADER: 6 registers, base 0x398, stride 0x1000
  • i3c_csr[6].I3C_EC.CtrlCfg.CONTROLLER_CONFIG: 6 registers, base 0x39C, stride 0x1000
  • i3c_csr[6].I3C_EC.TERMINATION_EXTCAP_HEADER: 6 registers, base 0x3A0, stride 0x1000
  • i3c_csr[6].DAT.DAT_MEMORY[128]: 768 registers, base 0x400 (i3c_csr x6 stride 0x1000, DAT_MEMORY x128 stride 0x8)
  • i3c_csr[6].DCT.DCT_MEMORY[128]: 768 registers, base 0x800 (i3c_csr x6 stride 0x1000, DCT_MEMORY x128 stride 0x10)

Register List:

Table 1. OCA I3C Controller Wrapper Address Map register list
AddressNameAccessDescription
0x0 - 0x5000i3c_csr[6].I3CBase.HCI_VERSIONRIdentifies the implemented MIPI I3C HCI version.
0x4 - 0x5004i3c_csr[6].I3CBase.HC_CONTROLRWControls host-controller bus operation, mode selection, transaction abort, and Hot-Join handling.
0x8 - 0x5008i3c_csr[6].I3CBase.CONTROLLER_DEVICE_ADDRRWConfigures the controller dynamic address and indicates whether that address is valid.
0xC - 0x500Ci3c_csr[6].I3CBase.HC_CAPABILITIESRReports the host-controller capabilities implemented by this instance.
0x10 - 0x5010i3c_csr[6].I3CBase.RESET_CONTROLRWRequests a controller soft reset or selective PIO queue and FIFO resets. Reset requests are self-clearing.
0x14 - 0x5014i3c_csr[6].I3CBase.PRESENT_STATERReports current controller state, including active-controller bus ownership.
0x20 - 0x5020i3c_csr[6].I3CBase.INTR_STATUSRWReports host-controller error and exceptional-condition status.
0x24 - 0x5024i3c_csr[6].I3CBase.INTR_STATUS_ENABLERWEnables individual host-controller interrupt status sources.
0x28 - 0x5028i3c_csr[6].I3CBase.INTR_SIGNAL_ENABLERWRoutes enabled host-controller interrupt sources to the interrupt output.
0x2C - 0x502Ci3c_csr[6].I3CBase.INTR_FORCEWForces host-controller interrupts for software testing.
0x30 - 0x5030i3c_csr[6].I3CBase.DAT_SECTION_OFFSETRReports the Device Address Table section offset and size.
0x34 - 0x5034i3c_csr[6].I3CBase.DCT_SECTION_OFFSETRWConfigures the Device Characteristic Table section offset, size, and ENTDAA index.
0x38 - 0x5038i3c_csr[6].I3CBase.RING_HEADERS_SECTION_OFFSETR-
0x3C - 0x503Ci3c_csr[6].I3CBase.PIO_SECTION_OFFSETRReports the PIO section offset.
0x40 - 0x5040i3c_csr[6].I3CBase.EXT_CAPS_SECTION_OFFSETR-
0x4C - 0x504Ci3c_csr[6].I3CBase.INT_CTRL_CMDS_ENR-
0x58 - 0x5058i3c_csr[6].I3CBase.IBI_NOTIFY_CTRLRW-
0x5C - 0x505Ci3c_csr[6].I3CBase.IBI_DATA_ABORT_CTRLRW-
0x60 - 0x5060i3c_csr[6].I3CBase.DEV_CTX_BASE_LORW-
0x64 - 0x5064i3c_csr[6].I3CBase.DEV_CTX_BASE_HIRW-
0x68 - 0x5068i3c_csr[6].I3CBase.DEV_CTX_SGR-
0x80 - 0x5080i3c_csr[6].PIOControl.COMMAND_PORTWAccepts a 64-bit command descriptor as two consecutive 32-bit writes. The second write enqueues the descriptor.
0x84 - 0x5084i3c_csr[6].PIOControl.RESPONSE_PORTRReturns one 32-bit response descriptor from the response queue.
0x88 - 0x5088i3c_csr[6].PIOControl.TX_DATA_PORTWWrites transmit data to the TX FIFO. This port shares its address with the read-only RX data port.
0x88 - 0x5088i3c_csr[6].PIOControl.RX_DATA_PORTRReads received data from the RX FIFO. This port shares its address with the write-only TX data port.
0x8C - 0x508Ci3c_csr[6].PIOControl.IBI_PORTRReturns IBI status and payload data. Payload data is padded to a 4-byte boundary.
0x90 - 0x5090i3c_csr[6].PIOControl.QUEUE_THLD_CTRLRWConfigures command, response, and IBI queue thresholds as raw entry counts.
0x94 - 0x5094i3c_csr[6].PIOControl.DATA_BUFFER_THLD_CTRLRWConfigures TX and RX start and ready thresholds, each encoding 2^(N+1) entries.
0x98 - 0x5098i3c_csr[6].PIOControl.QUEUE_SIZERReports command, response, IBI, TX, and RX queue depths.
0x9C - 0x509Ci3c_csr[6].PIOControl.ALT_QUEUE_SIZERReports extended IBI and alternate response queue sizes.
0xA0 - 0x50A0i3c_csr[6].PIOControl.PIO_INTR_STATUSRWReports PIO queue-threshold and transfer-event interrupt status.
0xA4 - 0x50A4i3c_csr[6].PIOControl.PIO_INTR_STATUS_ENABLERWEnables individual PIO interrupt status sources.
0xA8 - 0x50A8i3c_csr[6].PIOControl.PIO_INTR_SIGNAL_ENABLERWRoutes enabled PIO interrupt sources to the interrupt output.
0xAC - 0x50ACi3c_csr[6].PIOControl.PIO_INTR_FORCEW-
0xB0 - 0x50B0i3c_csr[6].PIOControl.PIO_CONTROLRWControls run/stop and forced abort of enqueued commands.
0x100 - 0x5100i3c_csr[6].I3C_EC.SecFwRecoveryIf.EXTCAP_HEADERR-
0x104 - 0x5104i3c_csr[6].I3C_EC.SecFwRecoveryIf.PROT_CAP_0R-
0x108 - 0x5108i3c_csr[6].I3C_EC.SecFwRecoveryIf.PROT_CAP_1R-
0x10C - 0x510Ci3c_csr[6].I3C_EC.SecFwRecoveryIf.PROT_CAP_2RW-
0x110 - 0x5110i3c_csr[6].I3C_EC.SecFwRecoveryIf.PROT_CAP_3RW-
0x114 - 0x5114i3c_csr[6].I3C_EC.SecFwRecoveryIf.DEVICE_ID_0RW-
0x118 - 0x5118i3c_csr[6].I3C_EC.SecFwRecoveryIf.DEVICE_ID_1RW-
0x11C - 0x511Ci3c_csr[6].I3C_EC.SecFwRecoveryIf.DEVICE_ID_2RW-
0x120 - 0x5120i3c_csr[6].I3C_EC.SecFwRecoveryIf.DEVICE_ID_3RW-
0x124 - 0x5124i3c_csr[6].I3C_EC.SecFwRecoveryIf.DEVICE_ID_4RW-
0x128 - 0x5128i3c_csr[6].I3C_EC.SecFwRecoveryIf.DEVICE_ID_5RW-
0x12C - 0x512Ci3c_csr[6].I3C_EC.SecFwRecoveryIf.DEVICE_ID_RESERVEDR-
0x130 - 0x5130i3c_csr[6].I3C_EC.SecFwRecoveryIf.DEVICE_STATUS_0RW-
0x134 - 0x5134i3c_csr[6].I3C_EC.SecFwRecoveryIf.DEVICE_STATUS_1RW-
0x138 - 0x5138i3c_csr[6].I3C_EC.SecFwRecoveryIf.DEVICE_RESETRWFor devices which support reset, this register will reset the device or management entity
0x13C - 0x513Ci3c_csr[6].I3C_EC.SecFwRecoveryIf.RECOVERY_CTRLRW-
0x140 - 0x5140i3c_csr[6].I3C_EC.SecFwRecoveryIf.RECOVERY_STATUSRW-
0x144 - 0x5144i3c_csr[6].I3C_EC.SecFwRecoveryIf.HW_STATUSRW-
0x148 - 0x5148i3c_csr[6].I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_CTRL_0RW-
0x14C - 0x514Ci3c_csr[6].I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_CTRL_1RW-
0x150 - 0x5150i3c_csr[6].I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_STATUS_0R-
0x154 - 0x5154i3c_csr[6].I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_STATUS_1R-
0x158 - 0x5158i3c_csr[6].I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_STATUS_2R-
0x15C - 0x515Ci3c_csr[6].I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_STATUS_3R-
0x160 - 0x5160i3c_csr[6].I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_STATUS_4R-
0x164 - 0x5164i3c_csr[6].I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_RESERVEDR-
0x168 - 0x5168i3c_csr[6].I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_DATARIndirect memory access to address space configured in INDIRECT_FIFO_CTRL at the Head Pointer offset.
0x180 - 0x5180i3c_csr[6].I3C_EC.StdbyCtrlMode.EXTCAP_HEADERR-
0x184 - 0x5184i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_CONTROLRWConfigures standby-controller operation, dynamic-address-assignment methods, target transactions, and controller-role handoff.
0x188 - 0x5188i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_DEVICE_ADDRRWConfigures standby-controller dynamic and static addresses.
0x18C - 0x518Ci3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_CAPABILITIESRReports standby-controller capabilities.
0x190 - 0x5190i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_VIRTUAL_DEVICE_CHARRW-
0x194 - 0x5194i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_STATUSRW-
0x198 - 0x5198i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_DEVICE_CHARRW-
0x19C - 0x519Ci3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_DEVICE_PID_LORW-
0x1A0 - 0x51A0i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_INTR_STATUSRW-
0x1A4 - 0x51A4i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_VIRTUAL_DEVICE_PID_LORW-
0x1A8 - 0x51A8i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_INTR_SIGNAL_ENABLERWWhen set to 1'b1, and the corresponding interrupt status field is set in register
STBY_CR_INTR_STATUS, the Host Controller shall assert an interrupt to the Host.
0x1AC - 0x51ACi3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_INTR_FORCERWFor software testing, when set to 1'b1, forces the corresponding interrupt
to be sent to the Host, if the corresponding fields are set in register
STBY_CR_INTR_SIGNAL_ENABLE
0x1B0 - 0x51B0i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_GETCAPSRW-
0x1B4 - 0x51B4i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMSRWReports the defining byte of the last RSTACT CCC received and configures the reset recovery times.
0x1B8 - 0x51B8i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_VIRT_DEVICE_ADDRRW-
0x1BC - 0x51BCi3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_MWLR-
0x1C0 - 0x51C0i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_MRLR-
0x200 - 0x5200i3c_csr[6].I3C_EC.TTI.EXTCAP_HEADERR-
0x204 - 0x5204i3c_csr[6].I3C_EC.TTI.CONTROLRWControl Register
0x208 - 0x5208i3c_csr[6].I3C_EC.TTI.STATUSRStatus Register
0x20C - 0x520Ci3c_csr[6].I3C_EC.TTI.RESET_CONTROLRWReset Control for Queues and IBI Retry Counter
0x210 - 0x5210i3c_csr[6].I3C_EC.TTI.QUEUE_STATUSRDynamic queue full/empty status for debug and monitoring
0x214 - 0x5214i3c_csr[6].I3C_EC.TTI.DESC_QUEUE_DEPTHRCurrent number of entries in descriptor queues
0x218 - 0x5218i3c_csr[6].I3C_EC.TTI.DATA_QUEUE_DEPTHRCurrent number of DWORD entries in data queues
0x21C - 0x521Ci3c_csr[6].I3C_EC.TTI.IBI_QUEUE_DEPTHRCurrent number of entries in IBI queue
0x220 - 0x5220i3c_csr[6].I3C_EC.TTI.INTERRUPT_STATUSRWInterrupt Status.

How a bit is cleared depends on the bit:

- Auto-cleared by hardware on a specific access: RX_DESC_STAT, RX_DESC_THLD_STAT
and RX_DATA_THLD_STAT clear when software reads the corresponding RX queue; IBI_DONE
clears when software reads STATUS.LAST_IBI_STATUS. These bits are also write-1-to-clear,
but the normal servicing access clears them without an explicit write here.

- Write-1-to-clear only (no hardware auto-clear): TX_DESC_COMPLETE, TX_DESC_STAT,
TX_DESC_THLD_STAT, TX_DATA_THLD_STAT, IBI_THLD_STAT, and the not-implemented
TRANSFER_ERR_STAT, TRANSFER_ABORT_STAT, TX_DESC_TIMEOUT, RX_DESC_TIMEOUT. Write 1 to
the bit in this register to clear it.

- Read-only, hardware-driven level status that cannot be cleared by software:
PENDING_IBI and PENDING_INTERRUPT track live conditions.
0x224 - 0x5224i3c_csr[6].I3C_EC.TTI.INTERRUPT_ENABLERWInterrupt Enable
0x228 - 0x5228i3c_csr[6].I3C_EC.TTI.INTERRUPT_FORCERWInterrupt Force
0x22C - 0x522Ci3c_csr[6].I3C_EC.TTI.TARGET_ERR_CTRLRWTarget Error Detection Control. Set bits to enable error detection. Clear to disable.
0x230 - 0x5230i3c_csr[6].I3C_EC.TTI.TARGET_ERR_INTR_STATUSRWTarget Error Interrupt Status. Write 1 to clear individual bits.
0x234 - 0x5234i3c_csr[6].I3C_EC.TTI.TARGET_ERR_INTR_ENABLERWTarget Error Interrupt Enable. Set bits to enable corresponding interrupts.
0x238 - 0x5238i3c_csr[6].I3C_EC.TTI.TARGET_ERR_INTR_FORCERWTarget Error Interrupt Force. Set bits to force corresponding interrupts for testing.
0x23C - 0x523Ci3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_TE0RWCounts TE0 errors. Saturates at 255. Write 0 to clear.
0x240 - 0x5240i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_TE1RWCounts TE1 errors. Saturates at 255. Write 0 to clear.
0x244 - 0x5244i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_TE2RWCounts TE2 errors. Saturates at 255. Write 0 to clear.
0x248 - 0x5248i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_TE3RWCounts TE3 errors. Saturates at 255. Write 0 to clear.
0x24C - 0x524Ci3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_TE4RWCounts TE4 errors. Saturates at 255. Write 0 to clear.
0x250 - 0x5250i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_TE5RWCounts TE5 errors. Saturates at 255. Write 0 to clear.
0x254 - 0x5254i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_FRAMINGRWCounts framing errors. Saturates at 255. Write 0 to clear.
0x258 - 0x5258i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_RI_PECRWCounts Recovery Interface PEC errors. Saturates at 255. Write 0 to clear.
0x25C - 0x525Ci3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_RI_LENGTHRWCounts Recovery Interface length mismatch errors. Saturates at 255. Write 0 to clear.
0x260 - 0x5260i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_RI_READONLYRWCounts Recovery Interface write-to-read-only errors. Saturates at 255. Write 0 to clear.
0x264 - 0x5264i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_RI_UNSUPPORTEDRWCounts Recovery Interface unsupported command errors. Saturates at 255. Write 0 to clear.
0x268 - 0x5268i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_RI_RX_FIFO_OVERFLOWRWCounts Recovery Interface RX FIFO overflow errors. Saturates at 255. Write 0 to clear.
0x26C - 0x526Ci3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_RI_INDIRECT_FIFO_OVERFLOWRWCounts Recovery Interface INDIRECT FIFO overflow errors. Saturates at 255. Write 0 to clear.
0x270 - 0x5270i3c_csr[6].I3C_EC.TTI.RX_DESC_QUEUE_PORTRRX Descriptor Queue Port
0x274 - 0x5274i3c_csr[6].I3C_EC.TTI.RX_DATA_PORTRRX Data Port
0x278 - 0x5278i3c_csr[6].I3C_EC.TTI.TX_DESC_QUEUE_PORTWTX Descriptor Queue Port
0x27C - 0x527Ci3c_csr[6].I3C_EC.TTI.TX_DATA_PORTWTX Data Port
0x280 - 0x5280i3c_csr[6].I3C_EC.TTI.IBI_PORTWIBI Data Port
0x284 - 0x5284i3c_csr[6].I3C_EC.TTI.QUEUE_SIZERQueue Size
0x288 - 0x5288i3c_csr[6].I3C_EC.TTI.IBI_QUEUE_SIZERIBI Queue Size
0x28C - 0x528Ci3c_csr[6].I3C_EC.TTI.QUEUE_THLD_CTRLRWQueue Threshold Control
0x290 - 0x5290i3c_csr[6].I3C_EC.TTI.DATA_BUFFER_THLD_CTRLRWIBI Queue Threshold Control
0x300 - 0x5300i3c_csr[6].I3C_EC.SoCMgmtIf.EXTCAP_HEADERR-
0x304 - 0x5304i3c_csr[6].I3C_EC.SoCMgmtIf.SOC_MGMT_CONTROLRW-
0x308 - 0x5308i3c_csr[6].I3C_EC.SoCMgmtIf.SOC_MGMT_STATUSRW-
0x30C - 0x530Ci3c_csr[6].I3C_EC.SoCMgmtIf.REC_INTF_CFGRWConfigures the recovery interface and signals payload completion to the recovery handler.
0x310 - 0x5310i3c_csr[6].I3C_EC.SoCMgmtIf.REC_INTF_REG_W1C_ACCESSRW-
0x314 - 0x5314i3c_csr[6].I3C_EC.SoCMgmtIf.SOC_MGMT_RSVD_2RW-
0x318 - 0x5318i3c_csr[6].I3C_EC.SoCMgmtIf.SOC_MGMT_RSVD_3RW-
0x31C - 0x531Ci3c_csr[6].I3C_EC.SoCMgmtIf.SOC_PAD_CONFRW-
0x320 - 0x5320i3c_csr[6].I3C_EC.SoCMgmtIf.SOC_PAD_ATTRRW-
0x324 - 0x5324i3c_csr[6].I3C_EC.SoCMgmtIf.SOC_MGMT_FEATURE_2RW-
0x328 - 0x5328i3c_csr[6].I3C_EC.SoCMgmtIf.SOC_MGMT_FEATURE_3RW-
0x32C - 0x532Ci3c_csr[6].I3C_EC.SoCMgmtIf.T_R_REGRW-
0x330 - 0x5330i3c_csr[6].I3C_EC.SoCMgmtIf.T_F_REGRW-
0x334 - 0x5334i3c_csr[6].I3C_EC.SoCMgmtIf.T_SU_DAT_REGRW-
0x338 - 0x5338i3c_csr[6].I3C_EC.SoCMgmtIf.T_SU_DAT_I2C_REGRW-
0x33C - 0x533Ci3c_csr[6].I3C_EC.SoCMgmtIf.T_HD_DAT_REGRW-
0x340 - 0x5340i3c_csr[6].I3C_EC.SoCMgmtIf.T_HIGH_REGRW-
0x344 - 0x5344i3c_csr[6].I3C_EC.SoCMgmtIf.T_HIGH_OD_REGRW-
0x348 - 0x5348i3c_csr[6].I3C_EC.SoCMgmtIf.T_HIGH_INIT_OD_REGRW-
0x34C - 0x534Ci3c_csr[6].I3C_EC.SoCMgmtIf.T_HIGH_I2C_REGRW-
0x350 - 0x5350i3c_csr[6].I3C_EC.SoCMgmtIf.T_LOW_REGRW-
0x354 - 0x5354i3c_csr[6].I3C_EC.SoCMgmtIf.T_LOW_OD_REGRW-
0x358 - 0x5358i3c_csr[6].I3C_EC.SoCMgmtIf.T_LOW_I2C_REGRW-
0x35C - 0x535Ci3c_csr[6].I3C_EC.SoCMgmtIf.T_HD_STA_REGRW-
0x360 - 0x5360i3c_csr[6].I3C_EC.SoCMgmtIf.T_HD_STA_I2C_REGRW-
0x364 - 0x5364i3c_csr[6].I3C_EC.SoCMgmtIf.T_HD_RSTA_REGRW-
0x368 - 0x5368i3c_csr[6].I3C_EC.SoCMgmtIf.T_SU_STA_REGRW-
0x36C - 0x536Ci3c_csr[6].I3C_EC.SoCMgmtIf.T_SU_STA_I2C_REGRW-
0x370 - 0x5370i3c_csr[6].I3C_EC.SoCMgmtIf.T_SU_STO_REGRW-
0x374 - 0x5374i3c_csr[6].I3C_EC.SoCMgmtIf.T_SU_STO_I2C_REGRW-
0x378 - 0x5378i3c_csr[6].I3C_EC.SoCMgmtIf.T_DS_OD_REGRW-
0x37C - 0x537Ci3c_csr[6].I3C_EC.SoCMgmtIf.T_FREE_REGRW-
0x380 - 0x5380i3c_csr[6].I3C_EC.SoCMgmtIf.T_FREE_I2C_REGRW-
0x384 - 0x5384i3c_csr[6].I3C_EC.SoCMgmtIf.T_AVAL_REGRW-
0x388 - 0x5388i3c_csr[6].I3C_EC.SoCMgmtIf.T_IDLE_REGRW-
0x38C - 0x538Ci3c_csr[6].I3C_EC.SoCMgmtIf.HDR_TIMEOUT_EN_REGRW-
0x390 - 0x5390i3c_csr[6].I3C_EC.SoCMgmtIf.T_HDR_TIMEOUT_REGRW-
0x398 - 0x5398i3c_csr[6].I3C_EC.CtrlCfg.EXTCAP_HEADERR-
0x39C - 0x539Ci3c_csr[6].I3C_EC.CtrlCfg.CONTROLLER_CONFIGR-
0x3A0 - 0x53A0i3c_csr[6].I3C_EC.TERMINATION_EXTCAP_HEADERRRegister after the last EC must advertise ID == 0.
Termination register is added to guarantee that the discovery mechanism
reaches termination value.
0x400 - 0x57F8i3c_csr[6].DAT.DAT_MEMORY[128]RW-
0x800 - 0x5FF0i3c_csr[6].DCT.DCT_MEMORY[128]RHolds one Device Characteristic Table entry per device enumerated by ENTDAA.

Register Details:

i3c_csr[6].I3CBase.HCI_VERSION

Table 2. oca_i3c_wrap.i3c_csr[6].I3CBase.HCI_VERSION fields
BitsFieldAccessResetDescription
31:0VERSIONR0x120-

i3c_csr[6].I3CBase.HC_CONTROL

Table 3. oca_i3c_wrap.i3c_csr[6].I3CBase.HC_CONTROL fields
BitsFieldAccessResetDescription
31BUS_ENABLERW0x0Host Controller Bus Enable
30RESUMERW1C0x0Host Controller Resume:

0 - Controller is running

1 - Controller is suspended

Write 1 to resume Controller operations.
29ABORTRW0x0Host Controller Abort when set to 1
28:13Reserved--Reserved
12HALT_ON_CMD_SEQ_TIMEOUTRW0x0Halt on Command Sequence Timeout when set to 1
11:9Reserved--Reserved
8HOT_JOIN_CTRLRW0x0Hot-Join ACK/NACK Control:

0 - ACK Hot-Join request

1 - NACK Hot-Join request and send Broadcast CCC to disable Hot-Join
7I2C_DEV_PRESENTRW0x0I2C Device Present on Bus:

0 - pure I3C bus

1 - legacy I2C devices on the bus
6MODE_SELECTORR0x1DMA/PIO Mode Selector:

0 - DMA

1 - PIO
5Reserved--Reserved
4DATA_BYTE_ORDER_MODER0x0Data Byte Ordering Mode:

0 - Little Endian

1 - Big Endian
3AUTOCMD_DATA_RPTR0x0Auto-Command Data Report:

0 - coalesced reporting

1 - separated reporting
2:1Reserved--Reserved
0IBA_INCLUDERW0x0Include I3C Broadcast Address:

0 - skips I3C Broadcast Address for private transfers

1 - includes I3C Broadcast Address for private transfers

i3c_csr[6].I3CBase.CONTROLLER_DEVICE_ADDR

Table 4. oca_i3c_wrap.i3c_csr[6].I3CBase.CONTROLLER_DEVICE_ADDR fields
BitsFieldAccessResetDescription
31DYNAMIC_ADDR_VALIDRW0x0Dynamic Address is Valid:

0 - dynamic address is invalid

1 - dynamic address is valid
30:23Reserved--Reserved
22:16DYNAMIC_ADDRRW0x0Device Dynamic Address
15:0Reserved--Reserved

i3c_csr[6].I3CBase.HC_CAPABILITIES

Table 5. oca_i3c_wrap.i3c_csr[6].I3CBase.HC_CAPABILITIES fields
BitsFieldAccessResetDescription
31Reserved--Reserved
30SG_CAPABILITY_DC_ENR0x0Device context memory:

0 - must be physically continuous

1 - controller supports scatter-gather
29SG_CAPABILITY_IBI_ENR0x0DMA only: IBI status and IBI Data rings memory:

0 - must be physically continuous

1 - controller supports scatter-gather
28SG_CAPABILITY_CR_ENR0x0DMA only: Command and Response rings memory:

0 - must be physically continuous

1 - controller supports scatter-gather
27:22Reserved--Reserved
21:20CMD_SIZER0x0Size and structure of the Command Descriptor:

2'b0: 2 DWORDs,

all other reserved.
19:14Reserved--Reserved
13SCHEDULED_COMMANDS_ENR0x0Controller command scheduling:

0 - not supported

1 - supported
12IBI_CREDIT_COUNT_ENR0x0Controller IBI credit count:

0 - not supported

1 - supported
11IBI_DATA_ABORT_ENR0x0Controller IBI data abort:

0 - not supported

1 - supported
10CMD_CCC_DEFBYTER0x1CCC with defining byte:

0 - not supported

1 - supported
9:8Reserved--Reserved
7HDR_TS_ENR0x0HDR-Ternary transfers:

0 - not supported

1 - supported
6HDR_DDR_ENR0x0HDR-DDR transfers:

0 - not supported

1 - supported
5STANDBY_CR_CAPR0x0Switching from active to standby mode:

0 - not supported, this controller is always active on I3C

1- supported, this controller can hand off I3C to secondary controller
4Reserved--Reserved
3AUTO_COMMANDR0x0Automatic read command on IBI:

0 - not supported

1 - supported
2COMBO_COMMANDR0x0Controller combined command:

0 - not supported

1 - supported
1:0Reserved--Reserved

i3c_csr[6].I3CBase.RESET_CONTROL

Table 6. oca_i3c_wrap.i3c_csr[6].I3CBase.RESET_CONTROL fields
BitsFieldAccessResetDescription
31:6Reserved--Reserved
5IBI_QUEUE_RSTRW0x0Clear IBI queue from software. Valid only in PIO mode.
4RX_FIFO_RSTRW0x0Clear RX FIFO from software. Valid only in PIO mode.
3TX_FIFO_RSTRW0x0Clear TX FIFO from software. Valid only in PIO mode.
2RESP_QUEUE_RSTRW0x0Clear response queue from software. Valid only in PIO mode.
1CMD_QUEUE_RSTRW0x0Clear command queue from software. Valid only in PIO mode.
0SOFT_RSTRW0x0Reset controller from software. Not supported currently

i3c_csr[6].I3CBase.PRESENT_STATE

Table 7. oca_i3c_wrap.i3c_csr[6].I3CBase.PRESENT_STATE fields
BitsFieldAccessResetDescription
31:3Reserved--Reserved
2AC_CURRENT_OWNR0x0Controller I3C state:

0 - not bus owner

1 - bus owner
1:0Reserved--Reserved

i3c_csr[6].I3CBase.INTR_STATUS

Table 8. oca_i3c_wrap.i3c_csr[6].I3CBase.INTR_STATUS fields
BitsFieldAccessResetDescription
31:15Reserved--Reserved
14SCHED_CMD_MISSED_TICK_STATRW1C0x0Scheduled commands could be executed due to controller being busy.
13HC_ERR_CMD_SEQ_TIMEOUT_STATRW1C0x0Command timeout after prolonged stall.
12HC_WARN_CMD_SEQ_STALL_STATRW1C0x0Clock stalled due to lack of commands.
11HC_SEQ_CANCEL_STATRW1C0x0Controller had to cancel command sequence.
10HC_INTERNAL_ERR_STATRW1C0x0Controller internal unrecoverable error.
9:0Reserved--Reserved

i3c_csr[6].I3CBase.INTR_STATUS_ENABLE

Table 9. oca_i3c_wrap.i3c_csr[6].I3CBase.INTR_STATUS_ENABLE fields
BitsFieldAccessResetDescription
31:15Reserved--Reserved
14SCHED_CMD_MISSED_TICK_STAT_ENRW0x0Enable SCHED_CMD_MISSED_TICK_STAT monitoring.
13HC_ERR_CMD_SEQ_TIMEOUT_STAT_ENRW0x0Enable HC_ERR_CMD_SEQ_TIMEOUT_STAT monitoring.
12HC_WARN_CMD_SEQ_STALL_STAT_ENRW0x0Enable HC_WARN_CMD_SEQ_STALL_STAT monitoring.
11HC_SEQ_CANCEL_STAT_ENRW0x0Enable HC_SEQ_CANCEL_STAT monitoring.
10HC_INTERNAL_ERR_STAT_ENRW0x0Enable HC_INTERNAL_ERR_STAT monitoring.
9:0Reserved--Reserved

i3c_csr[6].I3CBase.INTR_SIGNAL_ENABLE

Table 10. oca_i3c_wrap.i3c_csr[6].I3CBase.INTR_SIGNAL_ENABLE fields
BitsFieldAccessResetDescription
31:15Reserved--Reserved
14SCHED_CMD_MISSED_TICK_SIGNAL_ENRW0x0Enable SCHED_CMD_MISSED_TICK_STAT interrupt.
13HC_ERR_CMD_SEQ_TIMEOUT_SIGNAL_ENRW0x0Enable HC_ERR_CMD_SEQ_TIMEOUT_STAT interrupt.
12HC_WARN_CMD_SEQ_STALL_SIGNAL_ENRW0x0Enable HC_WARN_CMD_SEQ_STALL_STAT interrupt.
11HC_SEQ_CANCEL_SIGNAL_ENRW0x0Enable HC_SEQ_CANCEL_STAT interrupt.
10HC_INTERNAL_ERR_SIGNAL_ENRW0x0Enable HC_INTERNAL_ERR_STAT interrupt.
9:0Reserved--Reserved

i3c_csr[6].I3CBase.INTR_FORCE

Table 11. oca_i3c_wrap.i3c_csr[6].I3CBase.INTR_FORCE fields
BitsFieldAccessResetDescription
31:15Reserved--Reserved
14SCHED_CMD_MISSED_TICK_FORCEW0x0Force SCHED_CMD_MISSED_TICK_STAT interrupt.
13HC_ERR_CMD_SEQ_TIMEOUT_FORCEW0x0Force HC_ERR_CMD_SEQ_TIMEOUT_STAT interrupt.
12HC_WARN_CMD_SEQ_STALL_FORCEW0x0Force HC_WARN_CMD_SEQ_STALL_STAT interrupt.
11HC_SEQ_CANCEL_FORCEW0x0Force HC_SEQ_CANCEL_STAT interrupt.
10HC_INTERNAL_ERR_FORCEW0x0Force HC_INTERNAL_ERR_STAT interrupt.
9:0Reserved--Reserved

i3c_csr[6].I3CBase.DAT_SECTION_OFFSET

Table 12. oca_i3c_wrap.i3c_csr[6].I3CBase.DAT_SECTION_OFFSET fields
BitsFieldAccessResetDescription
31:28ENTRY_SIZER0x0Individual DAT entry size.
0 - 2 DWRODs,
1:15 - reserved.
27:19Reserved--Reserved
18:12TABLE_SIZER0x7FMax number of DAT entries.
11:0TABLE_OFFSETR0x400DAT entry offset in respect to BASE address.

i3c_csr[6].I3CBase.DCT_SECTION_OFFSET

Table 13. oca_i3c_wrap.i3c_csr[6].I3CBase.DCT_SECTION_OFFSET fields
BitsFieldAccessResetDescription
31:28ENTRY_SIZER0x0Individual DCT entry size.

0 - 4 DWORDs,

1:15 - Reserved.
27:24Reserved--Reserved
23:19TABLE_INDEXRW0x0Index to DCT used during ENTDAA.
18:12TABLE_SIZER0x7FMax number of DCT entries.
11:0TABLE_OFFSETR0x800DCT entry offset in respect to BASE address.

i3c_csr[6].I3CBase.RING_HEADERS_SECTION_OFFSET

Table 14. oca_i3c_wrap.i3c_csr[6].I3CBase.RING_HEADERS_SECTION_OFFSET fields
BitsFieldAccessResetDescription
31:16Reserved--Reserved
15:0SECTION_OFFSETR0x0DMA ring headers section offset. Invalid if 0.

i3c_csr[6].I3CBase.PIO_SECTION_OFFSET

Table 15. oca_i3c_wrap.i3c_csr[6].I3CBase.PIO_SECTION_OFFSET fields
BitsFieldAccessResetDescription
31:16Reserved--Reserved
15:0SECTION_OFFSETR0x80PIO section offset. Invalid if 0.

i3c_csr[6].I3CBase.EXT_CAPS_SECTION_OFFSET

Table 16. oca_i3c_wrap.i3c_csr[6].I3CBase.EXT_CAPS_SECTION_OFFSET fields
BitsFieldAccessResetDescription
31:16Reserved--Reserved
15:0SECTION_OFFSETR0x100Extended Capabilities section offset. Invalid if 0.

i3c_csr[6].I3CBase.INT_CTRL_CMDS_EN

Table 17. oca_i3c_wrap.i3c_csr[6].I3CBase.INT_CTRL_CMDS_EN fields
BitsFieldAccessResetDescription
31:16Reserved--Reserved
15:1MIPI_CMDS_SUPPORTEDR0x35Bitmask of supported MIPI commands.
0ICC_SUPPORTR0x1Internal Control Commands:

1 - some or all internals commands sub-commands are supported,

0 - illegal.

i3c_csr[6].I3CBase.IBI_NOTIFY_CTRL

Table 18. oca_i3c_wrap.i3c_csr[6].I3CBase.IBI_NOTIFY_CTRL fields
BitsFieldAccessResetDescription
31:4Reserved--Reserved
3NOTIFY_IBI_REJECTEDRW0x0Notify about rejected IBI:

0 - do not enqueue rejected IBI,

1 = enqueue rejected IBI on IBI queue/ring.
2Reserved--Reserved
1NOTIFY_CRR_REJECTEDRW0x0Notify about rejected controller role request:

0 - do not enqueue rejected CRR,

1 = enqueue rejected CRR on IBI queue/ring.
0NOTIFY_HJ_REJECTEDRW0x0Notify about rejected hot-join:

0 - do not enqueue rejected HJ,

1 = enqueue rejected HJ on IBI queue/ring.

i3c_csr[6].I3CBase.IBI_DATA_ABORT_CTRL

Table 19. oca_i3c_wrap.i3c_csr[6].I3CBase.IBI_DATA_ABORT_CTRL fields
BitsFieldAccessResetDescription
31IBI_DATA_ABORT_MONRW0x0Enable/disable IBI monitoring logic.
30:21Reserved--Reserved
20:18MATCH_STATUS_TYPERW0x0Define which IBI should be aborted:

3'b000 - Regular IBI,

3'b100 - Autocmd IBI,

other values - not supported.
17:16AFTER_N_CHUNKSRW0x0Number of data chunks to be allowed before forced termination:

0 - immediate,

1:3 - delay by 1-3 data chunks.
15:8MATCH_IBI_IDRW0x0IBI target address:

[15:9] - device address,

[8] - must always be set to 1'b1
7:0Reserved--Reserved

i3c_csr[6].I3CBase.DEV_CTX_BASE_LO

Table 20. oca_i3c_wrap.i3c_csr[6].I3CBase.DEV_CTX_BASE_LO fields
BitsFieldAccessResetDescription
31:1Reserved--Reserved
0BASE_LORW0x0-

i3c_csr[6].I3CBase.DEV_CTX_BASE_HI

Table 21. oca_i3c_wrap.i3c_csr[6].I3CBase.DEV_CTX_BASE_HI fields
BitsFieldAccessResetDescription
31:1Reserved--Reserved
0BASE_HIRW0x0-

i3c_csr[6].I3CBase.DEV_CTX_SG

Table 22. oca_i3c_wrap.i3c_csr[6].I3CBase.DEV_CTX_SG fields
BitsFieldAccessResetDescription
31BLPR0x0Buffer vs list pointer in device context:

0 - continuous physical memory region,

1 - pointer to SG descriptor list.
30:16Reserved--Reserved
15:0LIST_SIZER0x0Number of SG entries.

i3c_csr[6].PIOControl.COMMAND_PORT

Table 23. oca_i3c_wrap.i3c_csr[6].PIOControl.COMMAND_PORT fields
BitsFieldAccessResetDescription
31:0COMMAND_DATAW--

i3c_csr[6].PIOControl.RESPONSE_PORT

Table 24. oca_i3c_wrap.i3c_csr[6].PIOControl.RESPONSE_PORT fields
BitsFieldAccessResetDescription
31:0RESPONSE_DATAR--

i3c_csr[6].PIOControl.TX_DATA_PORT

Table 25. oca_i3c_wrap.i3c_csr[6].PIOControl.TX_DATA_PORT fields
BitsFieldAccessResetDescription
31:0TX_DATAW--

i3c_csr[6].PIOControl.RX_DATA_PORT

Table 26. oca_i3c_wrap.i3c_csr[6].PIOControl.RX_DATA_PORT fields
BitsFieldAccessResetDescription
31:0RX_DATAR--

i3c_csr[6].PIOControl.IBI_PORT

Table 27. oca_i3c_wrap.i3c_csr[6].PIOControl.IBI_PORT fields
BitsFieldAccessResetDescription
31:0IBI_DATAR-Data Read from IBI Data Buffer.

The IBI Port is mapped to the IBI Data Queue.
IBI Data is always aligned to a 4-byte boundary and then put into the IBI Queue.
If the incoming data is not aligned to a 4-byte boundary,
then there will be extra (unused) bytes at the end of the transferred IBI data.
This can be determined from the value of field DATA_LENGTH in the IBI Status Descriptor.

i3c_csr[6].PIOControl.QUEUE_THLD_CTRL

Table 28. oca_i3c_wrap.i3c_csr[6].PIOControl.QUEUE_THLD_CTRL fields
BitsFieldAccessResetDescription
31:24IBI_STATUS_THLDRW0x1Triggers IBI_STATUS_THLD_STAT interrupt when IBI queue has N or more entries. Accepted values are 1:255
23:16IBI_DATA_SEGMENT_SIZERW0x1IBI Queue data segment size. Valida values are 1:63
15:8RESP_BUF_THLDRW0x1Triggers RESP_READY_STAT interrupt when RESP queue has N or more entries. Accepted values are 1:255
7:0CMD_EMPTY_BUF_THLDRW0x1Triggers CMD_QUEUE_READY_STAT interrupt when CMD queue has N or more free entries. Accepted values are 1:255

i3c_csr[6].PIOControl.DATA_BUFFER_THLD_CTRL

Table 29. oca_i3c_wrap.i3c_csr[6].PIOControl.DATA_BUFFER_THLD_CTRL fields
BitsFieldAccessResetDescription
31:27Reserved--Reserved
26:24RX_START_THLDRW0x1Postpone read command until RX queue has 2^(N+1) free entries
23:19Reserved--Reserved
18:16TX_START_THLDRW0x1Postpone write command until TX queue has 2^(N+1) entries
15:11Reserved--Reserved
10:8RX_BUF_THLDRW0x1Trigger RX_THLD_STAT interrupt when RX queue has 2^(N+1) or more entries
7:3Reserved--Reserved
2:0TX_BUF_THLDRW0x1Trigger TX_THLD_STAT interrupt when TX queue has 2^(N+1) or more free entries

i3c_csr[6].PIOControl.QUEUE_SIZE

Table 30. oca_i3c_wrap.i3c_csr[6].PIOControl.QUEUE_SIZE fields
BitsFieldAccessResetDescription
31:24TX_DATA_BUFFER_SIZER0x5TX queue size is equal to 2^(N+1), where N is this field value
23:16RX_DATA_BUFFER_SIZER0x5RX queue size is equal to 2^(N+1), where N is this field value
15:8IBI_STATUS_SIZER0x20IBI Queue size is equal to N
7:0CR_QUEUE_SIZER0x40Command/Response queue size is equal to N

i3c_csr[6].PIOControl.ALT_QUEUE_SIZE

Table 31. oca_i3c_wrap.i3c_csr[6].PIOControl.ALT_QUEUE_SIZE fields
BitsFieldAccessResetDescription
31:29Reserved--Reserved
28EXT_IBI_QUEUE_ENR0x01 indicates that IBI queue size is equal to 8*IBI_STATUS_SIZE
27:25Reserved--Reserved
24ALT_RESP_QUEUE_ENR0x1If set, response and command queues are not equal lengths, then
ALT_RESP_QUEUE_SIZE contains response queue size
23:8Reserved--Reserved
7:0ALT_RESP_QUEUE_SIZER0x20Valid only if ALT_RESP_QUEUE_EN is set. Contains response queue size

i3c_csr[6].PIOControl.PIO_INTR_STATUS

Table 32. oca_i3c_wrap.i3c_csr[6].PIOControl.PIO_INTR_STATUS fields
BitsFieldAccessResetDescription
31:10Reserved--Reserved
9TRANSFER_ERR_STATRW1C0x0Transfer error
8:6Reserved--Reserved
5TRANSFER_ABORT_STATRW1C0x0Transfer aborted
4RESP_READY_STATR0x0Response queue fulfils RESP_BUF_THLD
3CMD_QUEUE_READY_STATR0x0Command queue fulfils CMD_EMPTY_BUF_THLD
2IBI_STATUS_THLD_STATR0x0IBI queue fulfils IBI_STATUS_THLD
1RX_THLD_STATR0x0RX queue fulfils RX_BUF_THLD
0TX_THLD_STATR0x0TX queue fulfils TX_BUF_THLD

i3c_csr[6].PIOControl.PIO_INTR_STATUS_ENABLE

Table 33. oca_i3c_wrap.i3c_csr[6].PIOControl.PIO_INTR_STATUS_ENABLE fields
BitsFieldAccessResetDescription
31:10Reserved--Reserved
9TRANSFER_ERR_STAT_ENRW0x0Enable transfer error monitoring
8:6Reserved--Reserved
5TRANSFER_ABORT_STAT_ENRW0x0Enable transfer abort monitoring
4RESP_READY_STAT_ENRW0x0Enable response queue monitoring
3CMD_QUEUE_READY_STAT_ENRW0x0Enable command queue monitoring
2IBI_STATUS_THLD_STAT_ENRW0x0Enable IBI queue monitoring
1RX_THLD_STAT_ENRW0x0Enable RX queue monitoring
0TX_THLD_STAT_ENRW0x0Enable TX queue monitoring

i3c_csr[6].PIOControl.PIO_INTR_SIGNAL_ENABLE

Table 34. oca_i3c_wrap.i3c_csr[6].PIOControl.PIO_INTR_SIGNAL_ENABLE fields
BitsFieldAccessResetDescription
31:10Reserved--Reserved
9TRANSFER_ERR_SIGNAL_ENRW0x0Enable transfer error interrupt
8:6Reserved--Reserved
5TRANSFER_ABORT_SIGNAL_ENRW0x0Enable transfer abort interrupt
4RESP_READY_SIGNAL_ENRW0x0Enable response ready interrupt
3CMD_QUEUE_READY_SIGNAL_ENRW0x0Enable command queue interrupt
2IBI_STATUS_THLD_SIGNAL_ENRW0x0Enable IBI queue interrupt
1RX_THLD_SIGNAL_ENRW0x0Enable RX queue interrupt
0TX_THLD_SIGNAL_ENRW0x0Enable TX queue interrupt

i3c_csr[6].PIOControl.PIO_INTR_FORCE

Table 35. oca_i3c_wrap.i3c_csr[6].PIOControl.PIO_INTR_FORCE fields
BitsFieldAccessResetDescription
31:10Reserved--Reserved
9TRANSFER_ERR_FORCEW0x0Force transfer error
8:6Reserved--Reserved
5TRANSFER_ABORT_FORCEW0x0Force transfer aborted
4RESP_READY_FORCEW0x0Force response queue interrupt
3CMD_QUEUE_READY_FORCEW0x0Force command queue interrupt
2IBI_THLD_FORCEW0x0Force IBI queue interrupt
1RX_THLD_FORCEW0x0Force RX queue interrupt
0TX_THLD_FORCEW0x0Force TX queue interrupt

i3c_csr[6].PIOControl.PIO_CONTROL

Table 36. oca_i3c_wrap.i3c_csr[6].PIOControl.PIO_CONTROL fields
BitsFieldAccessResetDescription
31:3Reserved--Reserved
2ABORTRW0x0Stop current command descriptor execution forcefully and hold remaining commands.
1 - Request PIO Abort,
0 - Resume PIO execution
1RSRW0x0Run/Stop execution of enqueued commands.
When set to 0, it holds execution of enqueued commands and runs current command to completion.
1 - PIO Queue start request,
0 - PIO Queue stop request.
0ENABLERW0x1Enables PIO queues. When disabled, SW may not read from/write to PIO queues.
1 - PIO queue enable request,
0 - PIO queue disable request

i3c_csr[6].I3C_EC.SecFwRecoveryIf.EXTCAP_HEADER

Table 37. oca_i3c_wrap.i3c_csr[6].I3C_EC.SecFwRecoveryIf.EXTCAP_HEADER fields
BitsFieldAccessResetDescription
31:24Reserved--Reserved
23:8CAP_LENGTHR0x20Capability Structure Length in DWORDs
7:0CAP_IDR0xC0Extended Capability ID

i3c_csr[6].I3C_EC.SecFwRecoveryIf.PROT_CAP_0

Table 38. oca_i3c_wrap.i3c_csr[6].I3C_EC.SecFwRecoveryIf.PROT_CAP_0 fields
BitsFieldAccessResetDescription
31:0REC_MAGIC_STRING_0R0x2050434FMagic string 'OCP ' (1st part of 'OCP RECV') in ASCII code - '0x4f 0x43 0x50 0x20'

i3c_csr[6].I3C_EC.SecFwRecoveryIf.PROT_CAP_1

Table 39. oca_i3c_wrap.i3c_csr[6].I3C_EC.SecFwRecoveryIf.PROT_CAP_1 fields
BitsFieldAccessResetDescription
31:0REC_MAGIC_STRING_1R0x56434552Magic string 'RECV' (2nd part of 'OCP RECV') in ASCII code - '0x52 0x45 0x43 0x56'

i3c_csr[6].I3C_EC.SecFwRecoveryIf.PROT_CAP_2

Table 40. oca_i3c_wrap.i3c_csr[6].I3C_EC.SecFwRecoveryIf.PROT_CAP_2 fields
BitsFieldAccessResetDescription
31:16AGENT_CAPSRW0x0Agent capabilities:

* bit 0: Identification (DEVICE_ID structure)

* bit 1: Forced Recovery (From RESET)

* bit 2: Mgmt reset (From RESET)

* bit 3: Device Reset (From RESET)

* bit 4: Device status (DEVICE_STATUS)

* bit 5: Recovery memory access (INDIRECT_CTRL)

* bit 6: Local C-image support

* bit 7: Push C-image support

* bit 8: Interface isolation

* bit 9: Hardware status

* bit 10: Vendor command

* bit 11: Flashless boot (From RESET)

* bit 12: FIFO CMS support (INDIRECT_FIFO_CTRL)

* bits 13-15: Reserved
15:0REC_PROT_VERSIONRW0x0* Byte 0: Major version number = 0x1

* Byte 1: Minor version number = 0x1

i3c_csr[6].I3C_EC.SecFwRecoveryIf.PROT_CAP_3

Table 41. oca_i3c_wrap.i3c_csr[6].I3C_EC.SecFwRecoveryIf.PROT_CAP_3 fields
BitsFieldAccessResetDescription
31:24Reserved--Reserved
23:16HEARTBEAT_PERIODRW0x00-255: Heartbeat period, 2^x microseconds (us), 0 indicates not supported
15:8MAX_RESP_TIMERW0x00-255: Maximum response time in 2^x microseconds(us).
7:0NUM_OF_CMS_REGIONSRW0x00-255: The total number of component memory space (CMS) regions a device supports. This number includes any logging, code and vendor defined regions

i3c_csr[6].I3C_EC.SecFwRecoveryIf.DEVICE_ID_0

Table 42. oca_i3c_wrap.i3c_csr[6].I3C_EC.SecFwRecoveryIf.DEVICE_ID_0 fields
BitsFieldAccessResetDescription
31:16DATARW0x0-
15:8VENDOR_SPECIFIC_STR_LENGTHRW0x00x0-0xFF: Total length of Vendor Specific String, 0 indicates not supported
7:0DESC_TYPERW0x0Based on table 8 from [DMTF PLDM FM]:

* 0x00: PCI Vendor

* 0x1: IANA

* 0x2: UUID

* 0x3: PnP Vendor

* 0x4: ACPI Vendor

* 0x5: IANA Enterprise Type

* 0x6-0xFE: Reserved

* 0xFF: NVMe-MI

i3c_csr[6].I3C_EC.SecFwRecoveryIf.DEVICE_ID_1

Table 43. oca_i3c_wrap.i3c_csr[6].I3C_EC.SecFwRecoveryIf.DEVICE_ID_1 fields
BitsFieldAccessResetDescription
31:0DATARW0x0-

i3c_csr[6].I3C_EC.SecFwRecoveryIf.DEVICE_ID_2

Table 44. oca_i3c_wrap.i3c_csr[6].I3C_EC.SecFwRecoveryIf.DEVICE_ID_2 fields
BitsFieldAccessResetDescription
31:0DATARW0x0-

i3c_csr[6].I3C_EC.SecFwRecoveryIf.DEVICE_ID_3

Table 45. oca_i3c_wrap.i3c_csr[6].I3C_EC.SecFwRecoveryIf.DEVICE_ID_3 fields
BitsFieldAccessResetDescription
31:0DATARW0x0-

i3c_csr[6].I3C_EC.SecFwRecoveryIf.DEVICE_ID_4

Table 46. oca_i3c_wrap.i3c_csr[6].I3C_EC.SecFwRecoveryIf.DEVICE_ID_4 fields
BitsFieldAccessResetDescription
31:0DATARW0x0-

i3c_csr[6].I3C_EC.SecFwRecoveryIf.DEVICE_ID_5

Table 47. oca_i3c_wrap.i3c_csr[6].I3C_EC.SecFwRecoveryIf.DEVICE_ID_5 fields
BitsFieldAccessResetDescription
31:0DATARW0x0-

i3c_csr[6].I3C_EC.SecFwRecoveryIf.DEVICE_ID_RESERVED

Table 48. oca_i3c_wrap.i3c_csr[6].I3C_EC.SecFwRecoveryIf.DEVICE_ID_RESERVED fields
BitsFieldAccessResetDescription
31:0DATAR0x0-

i3c_csr[6].I3C_EC.SecFwRecoveryIf.DEVICE_STATUS_0

Table 49. oca_i3c_wrap.i3c_csr[6].I3C_EC.SecFwRecoveryIf.DEVICE_STATUS_0 fields
BitsFieldAccessResetDescription
31:16REC_REASON_CODERW0x0* 0x0: No Boot Failure detected (BFNF)

* 0x1: Generic hardware error (BFGHWE)

* 0x2: Generic hardware soft error (BFGSE) - soft error may be recoverable

* 0x3: Self-test failure (BFSTF) (e.g., RSA self test failure, FIPs self test failure,, etc.)

* 0x4: Corrupted/missing critical data (BFCD)

* 0x5: Missing/corrupt key manifest (BFKMMC)

* 0x6: Authentication Failure on key manifest (BFKMAF)

* 0x7: Anti-rollback failure on key manifest (BFKIAR)

* 0x8: Missing/corrupt boot loader (first mutable code) firmware image (BFFIMC)

* 0x9: Authentication failure on boot loader ( 1st mutable code) firmware image (BFFIAF)

* 0xA: Anti-rollback failure boot loader (1st mutable code) firmware image (BFFIAR)

* 0xB: Missing/corrupt main/management firmware image (BFMFMC)

* 0xC: Authentication Failure main/management firmware image (BFMFAF)

* 0xD: Anti-rollback Failure main/management firmware image (BFMFAR)

* 0xE: Missing/corrupt recovery firmware (BFRFMC)

* 0xF: Authentication Failure recovery firmware (BFRFAF)

* 0x10: Anti-rollback Failure on recovery firmware (BFRFAR)

* 0x11: Forced Recovery (FR)

* 0x12: Flashless/Streaming Boot (FSB)

* 0x13-0x7F: Reserved

* 0x80-0xFF: Vendor Unique Boot Failure Codes
15:8PROT_ERRORRW RC0x0* 0x0: No Protocol Error

* 0x1: Unsupported/Write Command - command is not support or a write to a RO command

* 0x2: Unsupported Parameter

* 0x3: Length write error (length of write command is incorrect)

* 0x4: CRC Error (if supported)

* 0x5-0xFE: Reserved

* 0xFF: General Protocol Error - catch all unclassified errors
7:0DEV_STATUSRW0x0* 0x0: Status Pending (Recover Reason Code not populated)

* 0x1: Device healthy (Recover Reason Code not populated)

* 0x2: Device Error (“soft” error or other error state) - (Recover Reason Code not populated)

* 0x3: Recovery mode - ready to accept recovery image - (Recover Reason Code populated)

* 0x4: Recovery Pending (waiting for activation) - (Recover Reason Code populated)

* 0x5: Running Recovery Image ( Recover Reason Code not populated)

* 0x6-0xD: Reserved

* 0xE: Boot Failure (Recover Reason Code populated)

* 0xF: Fatal Error (Recover Reason Code not populated)

* 0x10-FF:Reserved

i3c_csr[6].I3C_EC.SecFwRecoveryIf.DEVICE_STATUS_1

Table 50. oca_i3c_wrap.i3c_csr[6].I3C_EC.SecFwRecoveryIf.DEVICE_STATUS_1 fields
BitsFieldAccessResetDescription
31:25VENDOR_STATUSRW0x0-
24:16VENDOR_STATUS_LENGTHRW0x00-248: Length in bytes of just VENDOR_STATUS. Zero indicates no vendor status and zero additional bytes.
15:0HEARTBEATRW0x00-4095: Incrementing number (counter wraps)

i3c_csr[6].I3C_EC.SecFwRecoveryIf.DEVICE_RESET

Table 51. oca_i3c_wrap.i3c_csr[6].I3C_EC.SecFwRecoveryIf.DEVICE_RESET fields
BitsFieldAccessResetDescription
31:24Reserved--Reserved
23:16IF_CTRLRW0x0* 0x0: Disable Interface mastering

* 0x1: Enable Interface mastering
15:8FORCED_RECOVERYRW0x0* 0x0: No forced recovery

* 0x01-0xD: Reserved

* 0xE: Enter flashless boot mode on next platform reset

* 0xF: Enter recovery mode on next platform reset

* 0x10-FF: Reserved
7:0RESET_CTRLRW1C0x0* 0x0: No reset

* 0x1: Reset Device (PCIe Fundamental Reset or equivalent. This is likely bus disruptive)

* 0x2: Reset Management. This reset will reset the management subsystem. If supported, this reset MUST not be bus disruptive (cause re-enumeration)

* 0x3-FF: Reserved

i3c_csr[6].I3C_EC.SecFwRecoveryIf.RECOVERY_CTRL

Table 52. oca_i3c_wrap.i3c_csr[6].I3C_EC.SecFwRecoveryIf.RECOVERY_CTRL fields
BitsFieldAccessResetDescription
31:24Reserved--Reserved
23:16ACTIVATE_REC_IMGRW1C0x0* 0x0: do not activate recovery image - after activation device will report this code.

* 0xF: Activate recovery image

* 0x10-FF-reserved
15:8REC_IMG_SELRW0x0* 0x0: No operation

* 0x1: Use Recovery Image from memory window (CMS)

* 0x2: Use Recovery Image stored on device (C-image)

* 0x3-FF: reserved
7:0CMSRW0x0* 0-255: Selects a component memory space where the recovery image is. 0 is the default

i3c_csr[6].I3C_EC.SecFwRecoveryIf.RECOVERY_STATUS

Table 53. oca_i3c_wrap.i3c_csr[6].I3C_EC.SecFwRecoveryIf.RECOVERY_STATUS fields
BitsFieldAccessResetDescription
31:16Reserved--Reserved
15:8VENDOR_SPECIFIC_STATUSRW0x0-
7:4REC_IMG_INDEXRW0x0-
3:0DEV_REC_STATUSRW0x0* 0x0: Not in recovery mode

* 0x1: Awaiting recovery image

* 0x2: Booting recovery image

* 0x3: Recovery successful

* 0xc: Recovery failed

* 0xd: Recovery image authentication error

* 0xe: Error entering Recovery mode (might be administratively disabled)

* 0xf: Invalid component address space

i3c_csr[6].I3C_EC.SecFwRecoveryIf.HW_STATUS

Table 54. oca_i3c_wrap.i3c_csr[6].I3C_EC.SecFwRecoveryIf.HW_STATUS fields
BitsFieldAccessResetDescription
31:24VENDOR_HW_STATUS_LENRW0x00-251: Length in bytes of Vendor Specific Hardware Status.
23:16CTEMPRW0x0Current temperatureof device in degrees Celsius: Compatible with NVMe-MI command code 0 offset 3.

* 0x00-0x7e: 0 to 126 C

* 0x7f: 127 C or higher

* 0x80: no temperature data, or data is older than 5 seconds

* 0x81: temperature sensor failure

* 0x82-0x83: reserved

* 0xc4: -60 C or lower

* 0xc5-0xff: -59 to -1 C (in two's complement)
15:8VENDOR_HW_STATUSRW0x0-
7:3RESERVED_7_3RW0x0-
2FATAL_ERRRW0x0-
1SOFT_ERRRW0x0Hardware Soft Error (may need reset to clear)
0TEMP_CRITICALRW0x0Device temperature is critical (may need reset to clear)

i3c_csr[6].I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_CTRL_0

Table 55. oca_i3c_wrap.i3c_csr[6].I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_CTRL_0 fields
BitsFieldAccessResetDescription
31:16Reserved--Reserved
15:8RESETRW0x0Reset (Write 1 Clear):

* 0x0: idle

* 0x1: reset Write Index and Read Index to initial value.

* 0x2 to 0xFF: reserved
7:0CMSRW0x0This register selects a region within the device. Read/write access is through address
spaces. Each space represents a FIFO.
Component Memory Space (CMS):

* 0-255: Address region within a device.

i3c_csr[6].I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_CTRL_1

Table 56. oca_i3c_wrap.i3c_csr[6].I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_CTRL_1 fields
BitsFieldAccessResetDescription
31:0IMAGE_SIZERW0x0Image Size: Size of the image to be loaded in 4B units

i3c_csr[6].I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_STATUS_0

Table 57. oca_i3c_wrap.i3c_csr[6].I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_STATUS_0 fields
BitsFieldAccessResetDescription
31:11Reserved--Reserved
10:8REGION_TYPER0x0Memory Region Type:

* 0b000: Code space for recovery. (write only)

* 0b001: Log uses the defined debug format (read only)

* 0b100: Vendor Defined Region (write only)

* 0b101: Vendor Defined Region (read only)

* 0b111: Unsupported Region (address space out of range)
7:2Reserved--Reserved
1FULLR0x0If set, FIFO is full
0EMPTYR0x1If set, FIFO is empty

i3c_csr[6].I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_STATUS_1

Table 58. oca_i3c_wrap.i3c_csr[6].I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_STATUS_1 fields
BitsFieldAccessResetDescription
31:0WRITE_INDEXR0x0Offset incremented for each access by the Recovery Agent in 4B units

i3c_csr[6].I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_STATUS_2

Table 59. oca_i3c_wrap.i3c_csr[6].I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_STATUS_2 fields
BitsFieldAccessResetDescription
31:0READ_INDEXR0x0Offset incremented for each access by the device in 4B units

i3c_csr[6].I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_STATUS_3

Table 60. oca_i3c_wrap.i3c_csr[6].I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_STATUS_3 fields
BitsFieldAccessResetDescription
31:0FIFO_SIZER0x40Size of memory window specified in 4B units. Current implementation supports only a constant size of 64.

i3c_csr[6].I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_STATUS_4

Table 61. oca_i3c_wrap.i3c_csr[6].I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_STATUS_4 fields
BitsFieldAccessResetDescription
31:0MAX_TRANSFER_SIZER0x40Max size of the data payload in each read/write to INDIRECT_FIFO_DATA in 4B units

Enforced to 256 bytes (64 DWORDs) by Caliptra Subsystem Recovery Sequence

i3c_csr[6].I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_RESERVED

Table 62. oca_i3c_wrap.i3c_csr[6].I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_RESERVED fields
BitsFieldAccessResetDescription
31:0DATAR0x0-

i3c_csr[6].I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_DATA

Table 63. oca_i3c_wrap.i3c_csr[6].I3C_EC.SecFwRecoveryIf.INDIRECT_FIFO_DATA fields
BitsFieldAccessResetDescription
31:0DATAR0x0-

i3c_csr[6].I3C_EC.StdbyCtrlMode.EXTCAP_HEADER

Table 64. oca_i3c_wrap.i3c_csr[6].I3C_EC.StdbyCtrlMode.EXTCAP_HEADER fields
BitsFieldAccessResetDescription
31:24Reserved--Reserved
23:8CAP_LENGTHR0x20Capability Structure Length in DWORDs
7:0CAP_IDR0x12Extended Capability ID

i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_CONTROL

Table 65. oca_i3c_wrap.i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_CONTROL fields
BitsFieldAccessResetDescription
31:30STBY_CR_ENABLE_INITRW0x0Enables or disables the Secondary Controller:

2'b00 - DISABLED: Secondary Controller is disabled.

2'b01 - ACM_INIT: Secondary Controller is enabled,
but Host Controller initializes in Active Controller mode.

2'b10 - SCM_RUNNING: Secondary Controller operation is enabled,
Host Controller initializes in Standby Controller mode.

2'b11 - SCM_HOT_JOIN: Secondary Controller operation is enabled,
Host Controller conditionally becomes a Hot-Joining Device
to receive its Dynamic Address before operating in Standby Controller mode.
29:21Reserved--Reserved
20RSTACT_DEFBYTE_02RW0x0Controls whether I3C Secondary Controller Logic supports RSTACT CCC with
Defining Byte 0x02.

1'b0: NOT_SUPPORTED: Do not ACK Defining Byte 0x02

1'b1: HANDLE_INTR: Support Defining Byte 0x02
19:16Reserved--Reserved
15DAA_ENTDAA_ENABLERW0x0Indicates ENTDAA method is enabled.

1'b0: DISABLED: will not respond

1'b1: ENABLED: will respond
14DAA_SETDASA_ENABLERW0x0Indicates SETDASA method is enabled.

1'b0: DISABLED: will not respond

1'b1: ENABLED: will respond
13DAA_SETAASA_ENABLERW0x0Indicates SETAASA method is enabled.

1'b0: DISABLED: will not respond

1'b1: ENABLED: will respond
12TARGET_XACT_ENABLERW0x1Indicates whether Read-Type/Write-Type transaction servicing is enabled, via
an I3C Target Transaction Interface to software (Section 6.17.3).

1'b0: DISABLED: not available

1'b1: ENABLED: available for software
11Reserved--Reserved
10:8BAST_CCC_IBI_RINGRW0x0Indicates which Ring Bundle will be used to capture Broadcast CCC data sent by the Active Controller.
The Ring Bundle must be configured and enabled, and its IBI Ring Pair must also be initialized and ready to receive data.
7:6Reserved--Reserved
5CR_REQUEST_SENDW0x0Write of 1'b1 to this field shall instruct the Secondary Controller Logic
to attempt to send a Controller Role Request to the I3C Bus.
4HANDOFF_DEEP_SLEEPRW WS0x0If this field has a value of 1'b1, then the Secondary Controller Logic shall
report a return from Deep Sleep state to the Active Controller.
Writing 1'b1 to this bit is sticky. This field shall automatically clear to 1'b0
after accepting the Controller Role and transitioning to Active Controller mode.
3PRIME_ACCEPT_GETACCCRRW0x0-
2ACR_FSM_OP_SELECTRW0x0-
1HANDOFF_DELAY_NACKRW0x0-
0PENDING_RX_NACKRW0x0-

i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_DEVICE_ADDR

Table 66. oca_i3c_wrap.i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_DEVICE_ADDR fields
BitsFieldAccessResetDescription
31DYNAMIC_ADDR_VALIDRW0x0Indicates whether or not the value in the DYNAMIC_ADDR field is valid.
1'b0: DYNAMIC_ADDR field is not valid
1'b1: DYNAMIC_ADDR field is valid
30:23Reserved--Reserved
22:16DYNAMIC_ADDRRW0x0Contains the Host Controller Device’s Dynamic Address.
15STATIC_ADDR_VALIDRW0x0Indicates whether or not the value in the STATIC_ADDR field is valid.

1'b0: The Static Address field is not valid

1'b1: The Static Address field is valid
14:7Reserved--Reserved
6:0STATIC_ADDRRW0x0This field contains the Host Controller Device’s Static Address.

i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_CAPABILITIES

Table 67. oca_i3c_wrap.i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_CAPABILITIES fields
BitsFieldAccessResetDescription
31:16Reserved--Reserved
15DAA_ENTDAA_SUPPORTR0x0Defines whether Dynamic Address Assignment with ENTDAA CCC is supported.

1'b0: DISABLED: Not supported

1'b1: ENABLED: Supported
14DAA_SETDASA_SUPPORTR0x1Defines whether Dynamic Address Assignment with SETDASA CCC (using Static Address) is supported.

1'b0: DISABLED: Not supported

1'b1: ENABLED: Supported
13DAA_SETAASA_SUPPORTR0x1Defines whether Dynamic Address Assignment with SETAASA CCC (using Static Address) is supported.

1'b0: DISABLED: Not supported

1'b1: ENABLED: Supported
12TARGET_XACT_SUPPORTR0x1Defines whether an I3C Target Transaction Interface is supported.

1'b0: DISABLED: Not supported

1'b1: ENABLED: Supported via vendor-defined Extended Capability structure
11:6Reserved--Reserved
5SIMPLE_CRR_SUPPORTR0x0-
4:0Reserved--Reserved

i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_VIRTUAL_DEVICE_CHAR

Table 68. oca_i3c_wrap.i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_VIRTUAL_DEVICE_CHAR fields
BitsFieldAccessResetDescription
31:29BCR_FIXEDRW0x1Bus Characteristics, Fixed Part.

Reset value is set to 3'b001, because this device is an I3C Target,
which supports extended capabilities.

This field is Read-Only while the STBY_CR_ENABLE_INIT field in register
STBY_CR_CONTROL is not zero.
28:24BCR_VARRW0x10Bus Characteristics, Variable Part.

Reset value is set to 5'b10000, because this device:


- [bit4] is a Virtual Target

- [bit3] is not Offline Capable

- [bit2] does not apply due to bit1

- [bit1] is not capable of IBI requests

- [bit0] has no speed limitation

This field is Read-Only while the STBY_CR_ENABLE_INIT field in register
STBY_CR_CONTROL is not zero.
23:16DCRRW0xBDDevice Characteristics Register. Value represents an OCP Recovery Device.

This field is Read-Only while the STBY_CR_ENABLE_INIT field in register
STBY_CR_CONTROL is not zero.
15:1PID_HIRW0x7FFFHigh part of the 48-bit Target Device Provisioned ID.

This field is Read-Only while the STBY_CR_ENABLE_INIT field in register
STBY_CR_CONTROL is not zero.
0Reserved--Reserved

i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_STATUS

Table 69. oca_i3c_wrap.i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_STATUS fields
BitsFieldAccessResetDescription
31:9Reserved--Reserved
8HJ_REQ_STATUSRW0x0-
7:5SIMPLE_CRR_STATUSRW0x0-
4:3Reserved--Reserved
2AC_CURRENT_OWNRW0x0-
1:0Reserved--Reserved

i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_DEVICE_CHAR

Table 70. oca_i3c_wrap.i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_DEVICE_CHAR fields
BitsFieldAccessResetDescription
31:29BCR_FIXEDRW0x1Bus Characteristics, Fixed Part.

Reset value is set to 3'b001, because this device is an I3C Target,
which supports extended capabilities

This field is Read-Only while the STBY_CR_ENABLE_INIT field in register
STBY_CR_CONTROL is not zero.
28:24BCR_VARRW0x16Bus Characteristics, Variable Part.

Reset value is set to 5'b10110, because this device:


- [bit4] exposes a Virtual Target

- [bit3] is not Offline Capable

- [bit2] (always) uses the MDB in the IBI Payload

- [bit1] is capable of IBI requests

- [bit0] has no speed limitation

This field is Read-Only while the STBY_CR_ENABLE_INIT field in register
STBY_CR_CONTROL is not zero.
23:16DCRRW0xBDDevice Characteristics Register. Value represents an OCP Recovery Device.

This field is Read-Only while the STBY_CR_ENABLE_INIT field in register
STBY_CR_CONTROL is not zero.
15:1PID_HIRW0x7FFFHigh part of the 48-bit Target Device Provisioned ID.

This field is Read-Only while the STBY_CR_ENABLE_INIT field in register
STBY_CR_CONTROL is not zero.
0Reserved--Reserved

i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_DEVICE_PID_LO

Table 71. oca_i3c_wrap.i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_DEVICE_PID_LO fields
BitsFieldAccessResetDescription
31:0PID_LORW0x5A00A5Low part of the 48-bit Target Device Provisioned ID.

This field is Read-Only while the STBY_CR_ENABLE_INIT field in register
STBY_CR_CONTROL is not zero.

i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_INTR_STATUS

Table 72. oca_i3c_wrap.i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_INTR_STATUS fields
BitsFieldAccessResetDescription
31:20Reserved--Reserved
19CCC_FATAL_RSTDAA_ERR_STATRW0x0-
18CCC_UNHANDLED_NACK_STATRW0x0-
17CCC_PARAM_MODIFIED_STATRW0x0-
16STBY_CR_OP_RSTACT_STATRW0x0The Host Controller shall write 1'b1 to this field to indicate that the
Secondary Controller received a RSTACT CCC from the Active Controller, followed
by the Target Reset Pattern.
15Reserved--Reserved
14STBY_CR_ACCEPT_ERR_STATRW0x0-
13STBY_CR_ACCEPT_OK_STATRW0x0-
12STBY_CR_ACCEPT_NACKED_STATRW0x0-
11STBY_CR_DYN_ADDR_STATRW0x0-
10CRR_RESPONSE_STATRW0x0-
9:4Reserved--Reserved
3ACR_HANDOFF_ERR_M3_STATRW0x0-
2ACR_HANDOFF_ERR_FAIL_STATRW0x0-
1ACR_HANDOFF_OK_PRIMED_STATRW0x0-
0ACR_HANDOFF_OK_REMAIN_STATRW0x0-

i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_VIRTUAL_DEVICE_PID_LO

Table 73. oca_i3c_wrap.i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_VIRTUAL_DEVICE_PID_LO fields
BitsFieldAccessResetDescription
31:0PID_LORW0x5A10A5Low part of the 48-bit Target Virtual Device Provisioned ID.

This field is Read-Only while the STBY_CR_ENABLE_INIT field in register
STBY_CR_CONTROL is not zero.

i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_INTR_SIGNAL_ENABLE

Table 74. oca_i3c_wrap.i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_INTR_SIGNAL_ENABLE fields
BitsFieldAccessResetDescription
31:20Reserved--Reserved
19CCC_FATAL_RSTDAA_ERR_SIGNAL_ENRW0x0-
18CCC_UNHANDLED_NACK_SIGNAL_ENRW0x0-
17CCC_PARAM_MODIFIED_SIGNAL_ENRW0x0-
16STBY_CR_OP_RSTACT_SIGNAL_ENRW0x0-
15Reserved--Reserved
14STBY_CR_ACCEPT_ERR_SIGNAL_ENRW0x0-
13STBY_CR_ACCEPT_OK_SIGNAL_ENRW0x0-
12STBY_CR_ACCEPT_NACKED_SIGNAL_ENRW0x0-
11STBY_CR_DYN_ADDR_SIGNAL_ENRW0x0-
10CRR_RESPONSE_SIGNAL_ENRW0x0-
9:4Reserved--Reserved
3ACR_HANDOFF_ERR_M3_SIGNAL_ENRW0x0-
2ACR_HANDOFF_ERR_FAIL_SIGNAL_ENRW0x0-
1ACR_HANDOFF_OK_PRIMED_SIGNAL_ENRW0x0-
0ACR_HANDOFF_OK_REMAIN_SIGNAL_ENRW0x0-

i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_INTR_FORCE

Table 75. oca_i3c_wrap.i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_INTR_FORCE fields
BitsFieldAccessResetDescription
31:20Reserved--Reserved
19CCC_FATAL_RSTDAA_ERR_FORCERW0x0-
18CCC_UNHANDLED_NACK_FORCERW0x0-
17CCC_PARAM_MODIFIED_FORCERW0x0-
16STBY_CR_OP_RSTACT_FORCEW0x0-
15Reserved--Reserved
14STBY_CR_ACCEPT_ERR_FORCERW0x0-
13STBY_CR_ACCEPT_OK_FORCERW0x0-
12STBY_CR_ACCEPT_NACKED_FORCERW0x0-
11STBY_CR_DYN_ADDR_FORCERW0x0-
10CRR_RESPONSE_FORCERW0x0-
9:0Reserved--Reserved

i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_GETCAPS

Table 76. oca_i3c_wrap.i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_GETCAPS fields
BitsFieldAccessResetDescription
31:12Reserved--Reserved
11:8F2_CRCAP2_DEV_INTERACTRW0x0-
7:3Reserved--Reserved
2:0F2_CRCAP1_BUS_CONFIGRW0x0-

i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS

Table 77. oca_i3c_wrap.i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_CCC_CONFIG_RSTACT_PARAMS fields
BitsFieldAccessResetDescription
31RESET_DYNAMIC_ADDRRW0x1If set to 1'b1, then the Secondary Controller Logic must clear its Dynamic
Address in register STBY_CR_DEVICE_ADDR after receiving
a Target Reset Pattern that followed a Broadcast or Direct SET RSTACT CCC sent
to the Dynamic Address, with Defining Byte 0x01 or 0x02.
Requires support for Dynamic Address Assignment with at least one supported
method, such as the ENTDAA CCC, with field DAA_ENTDAA_ENABLE set to 1'b1 in
register STBY_CR_CONTROL.
If field ACR_FSM_OP_SELECT in register STBY_CR_CONTROL is set to 1'b1, then
this field shall be cleared (i.e., readiness to accept the Controller Role
shall be revoked) with this Target Reset Pattern.
30:24Reserved--Reserved
23:16RESET_TIME_TARGETRW0x0For Direct GET CCC, this field is returned for Defining Byte 0x82.
15:8RESET_TIME_PERIPHERALRW0x0For Direct GET CCC, this field is returned for Defining Byte 0x81.
7:0RST_ACTIONR0x1Contains the Defining Byte received with the last Direct SET CCC sent by the Active Controller. If not armed (START or RSTACT with unsupported defining byte) set to spec default 0x1.

i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_VIRT_DEVICE_ADDR

Table 78. oca_i3c_wrap.i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_VIRT_DEVICE_ADDR fields
BitsFieldAccessResetDescription
31VIRT_DYNAMIC_ADDR_VALIDRW0x0Indicates whether or not the value in the VIRT_DYNAMIC_ADDR field is valid.
1'b0: VIRT_DYNAMIC_ADDR field is not valid
1'b1: VIRT_DYNAMIC_ADDR field is valid
30:23Reserved--Reserved
22:16VIRT_DYNAMIC_ADDRRW0x0Contains the Controller Virtual Device’s Dynamic Address.
15VIRT_STATIC_ADDR_VALIDRW0x0Indicates whether or not the value in the VIRT_STATIC_ADDR field is valid.

1'b0: The Virtual Device Static Address field is not valid

1'b1: The Virtual Device Static Address field is valid
14:7Reserved--Reserved
6:0VIRT_STATIC_ADDRRW0x0This field contains the Host Controller Device’s Static Address.

i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_MWL

Table 79. oca_i3c_wrap.i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_MWL fields
BitsFieldAccessResetDescription
31:16Reserved--Reserved
15:0MWLR0x100This field contains the maximum write length (MWL) (read-only)

i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_MRL

Table 80. oca_i3c_wrap.i3c_csr[6].I3C_EC.StdbyCtrlMode.STBY_CR_MRL fields
BitsFieldAccessResetDescription
31:24Reserved--Reserved
23:16IBILR0x10This field contains the IBI payload size (IBIL) (read-only)
15:0MRLR0x100This field contains the maximum read length (MRL) (read-only)

i3c_csr[6].I3C_EC.TTI.EXTCAP_HEADER

Table 81. oca_i3c_wrap.i3c_csr[6].I3C_EC.TTI.EXTCAP_HEADER fields
BitsFieldAccessResetDescription
31:24Reserved--Reserved
23:8CAP_LENGTHR0x40Capability Structure Length in DWORDs
7:0CAP_IDR0xC4Extended Capability ID

i3c_csr[6].I3C_EC.TTI.CONTROL

Table 82. oca_i3c_wrap.i3c_csr[6].I3C_EC.TTI.CONTROL fields
BitsFieldAccessResetDescription
31:16Reserved--Reserved
15:13IBI_RETRY_NUMRW0x0Number of times the Target Device will try to request an IBI before giving up.

Values:

0x0 - Device will never retry.

0x1-0x6 - Device will retry this many times.

0x7 - Device will retry indefinitely until the Active Controller sets
DISINT bit in the DISEC command.
12IBI_ENRW0x1Enable the IBI queue servicing.

Values:

0x0 - Device will not service the IBI queue.

0x1 - Device will send IBI requests onto the bus, if possible.
11CRR_ENRW0x0Enable Controller Role Request.

Values:

0x0 - Device is allowed to perform Controller Role Request.

0x1 - Device is not allowed to perform Controller Role Request.
10HJ_ENRW0x1Enable Hot-Join capability.

Values:

0x0 - Device is allowed to attempt Hot-Join.

0x1 - Device is not allowed to attempt Hot-Join.
9:0Reserved--Reserved

i3c_csr[6].I3C_EC.TTI.STATUS

Table 83. oca_i3c_wrap.i3c_csr[6].I3C_EC.TTI.STATUS fields
BitsFieldAccessResetDescription
31:15Reserved--Reserved
14:12LAST_IBI_STATUSR0x0Status of last IBI. Should be read after IBI_DONE interrupt.

Values:

000 - Success: IBI was transmitted and ACK'd by the Active Controller.
001 - FailureNack: Active Controller NACK'd the IBI before any data was sent.
The device will retry sending the IBI as long as permitted by the retry counter.
010 - FailurePartialData: Active Controller NACK'd the IBI after data was
partially sent. The remaining part of data in the IBI queue is considered
corrupted and will be discarded.
011 - FailureRetry: IBI could not be serviced due to reached retry count.
100 - FailureArbitration:: IBI could not be serviced as arbitration was lost
during the address header. The device will retry sending the IBI as long as
permitted by the retry counter.
11:9Reserved--Reserved
8PROTOCOL_ERRORR0x0Protocol error occurred in the past. This field can only be reset
by the Controller, if it issues the GETSTATUS CCC.

Values:

0 - no error occurred

1 - generic protocol error occurred in the past. It will be set until reception
of the next GETSTATUS command.
7:0Reserved--Reserved

i3c_csr[6].I3C_EC.TTI.RESET_CONTROL

Table 84. oca_i3c_wrap.i3c_csr[6].I3C_EC.TTI.RESET_CONTROL fields
BitsFieldAccessResetDescription
31:7Reserved--Reserved
6IBI_RETRY_CTR_RSTW 1P0x0TTI IBI Retry Counter Software Reset
5IBI_QUEUE_RSTRW0x0TTI IBI Queue Buffer Software Reset
4RX_DATA_RSTRW0x0TTI RX Data Queue Buffer Software Reset
3TX_DATA_RSTRW0x0TTI TX Data Queue Buffer Software Reset. Also resets the tti_conv_Nto8 since first dword is immediately loaded into the converter and can't be cleared otherwise.
2RX_DESC_RSTRW0x0TTI RX Descriptor Queue Buffer Software Reset
1TX_DESC_RSTRW0x0TTI TX Descriptor Queue Buffer Software Reset
0SOFT_RSTRW0x0Target Core Software Reset

i3c_csr[6].I3C_EC.TTI.QUEUE_STATUS

Table 85. oca_i3c_wrap.i3c_csr[6].I3C_EC.TTI.QUEUE_STATUS fields
BitsFieldAccessResetDescription
31:10Reserved--Reserved
9IBI_QUEUE_EMPTYR0x1IBI Queue is empty
8IBI_QUEUE_FULLR0x0IBI Queue is full
7TX_DATA_QUEUE_EMPTYR0x1TX Data Queue is empty
6TX_DATA_QUEUE_FULLR0x0TX Data Queue is full
5RX_DATA_QUEUE_EMPTYR0x1RX Data Queue is empty
4RX_DATA_QUEUE_FULLR0x0RX Data Queue is full
3TX_DESC_QUEUE_EMPTYR0x1TX Descriptor Queue is empty
2TX_DESC_QUEUE_FULLR0x0TX Descriptor Queue is full
1RX_DESC_QUEUE_EMPTYR0x1RX Descriptor Queue is empty
0RX_DESC_QUEUE_FULLR0x0RX Descriptor Queue is full

i3c_csr[6].I3C_EC.TTI.DESC_QUEUE_DEPTH

Table 86. oca_i3c_wrap.i3c_csr[6].I3C_EC.TTI.DESC_QUEUE_DEPTH fields
BitsFieldAccessResetDescription
31:16Reserved--Reserved
15:8TX_DESC_QUEUE_DEPTHR0x0Number of entries in TX Descriptor Queue
7:0RX_DESC_QUEUE_DEPTHR0x0Number of entries in RX Descriptor Queue

i3c_csr[6].I3C_EC.TTI.DATA_QUEUE_DEPTH

Table 87. oca_i3c_wrap.i3c_csr[6].I3C_EC.TTI.DATA_QUEUE_DEPTH fields
BitsFieldAccessResetDescription
31:16Reserved--Reserved
15:8TX_DATA_QUEUE_DEPTHR0x0Number of DWORD entries in TX Data Queue
7:0RX_DATA_QUEUE_DEPTHR0x0Number of DWORD entries in RX Data Queue

i3c_csr[6].I3C_EC.TTI.IBI_QUEUE_DEPTH

Table 88. oca_i3c_wrap.i3c_csr[6].I3C_EC.TTI.IBI_QUEUE_DEPTH fields
BitsFieldAccessResetDescription
31:8Reserved--Reserved
7:0IBI_QUEUE_DEPTHR0x0Number of entries in IBI Queue

i3c_csr[6].I3C_EC.TTI.INTERRUPT_STATUS

Table 89. oca_i3c_wrap.i3c_csr[6].I3C_EC.TTI.INTERRUPT_STATUS fields
BitsFieldAccessResetDescription
31TRANSFER_ERR_STATRW1C0x0NOT IMPLEMENTED. Bus error occurred. Clear: write 1 to this bit in INTERRUPT_STATUS (no hardware auto-clear).
30:27Reserved--Reserved
26TX_DESC_COMPLETERW1C0x0Read Transaction on the I3C Bus completed. Clear: write 1 to this bit in INTERRUPT_STATUS (no hardware auto-clear).
25TRANSFER_ABORT_STATRW1C0x0NOT IMPLEMENTED. Bus aborted transaction. Clear: write 1 to this bit in INTERRUPT_STATUS (no hardware auto-clear).
24:21Reserved--Reserved
20PENDING_IBIR0x0At least one IBI is pending. Read-only, hardware-driven level status: it tracks the live IBI-pending condition and cannot be cleared by software (clears automatically when no IBI is pending).
19:16PENDING_INTERRUPTRW0x0Contains the interrupt number of any pending interrupt, or 0 if no interrupts are pending. This encoding allows for up to 15 numbered interrupts. If more than one interrupt is set, then the highest priority interrupt shall be returned. Read-only, hardware-driven level status: it cannot be cleared by software and updates as pending conditions change.
15:14Reserved--Reserved
13IBI_DONERW1C0x0IBI is done, check LAST_IBI_STATUS for result. Clear: auto-cleared by hardware when software reads STATUS.LAST_IBI_STATUS; writing 1 to this bit in INTERRUPT_STATUS also clears it.
12IBI_THLD_STATRW1C0x0TTI IBI Buffer Threshold Status, the Target Controller shall set this bit to 1 when the number of available entries in the TTI IBI Queue is >= the value defined in `TTI_IBI_THLD`. Clear: write 1 to this bit in INTERRUPT_STATUS (no hardware auto-clear).
11RX_DESC_THLD_STATRW1C0x0TTI RX Descriptor Buffer Threshold Status, the Target Controller shall set this bit to 1 when the number of available entries in the TTI RX Descriptor Queue is >= the value defined in `TTI_RX_DESC_THLD`. Clear: auto-cleared by hardware when software reads the RX Descriptor Queue; writing 1 to this bit in INTERRUPT_STATUS also clears it.
10TX_DESC_THLD_STATRW1C0x0TTI TX Descriptor Buffer Threshold Status, the Target Controller shall set this bit to 1 when the number of available entries in the TTI TX Descriptor Queue is >= the value defined in `TTI_TX_DESC_THLD`. Clear: write 1 to this bit in INTERRUPT_STATUS (no hardware auto-clear).
9RX_DATA_THLD_STATRW1C0x0TTI RX Data Buffer Threshold Status, the Target Controller shall set this bit to 1 when the number of entries in the TTI RX Data Queue is >= the value defined in `TTI_RX_DATA_THLD`. Clear: auto-cleared by hardware when software reads the RX Data Queue; writing 1 to this bit in INTERRUPT_STATUS also clears it.
8TX_DATA_THLD_STATRW1C0x0TTI TX Data Buffer Threshold Status, the Target Controller shall set this bit to 1 when the number of available entries in the TTI TX Data Queue is >= the value defined in `TTI_TX_DATA_THLD`. Clear: write 1 to this bit in INTERRUPT_STATUS (no hardware auto-clear).
7:4Reserved--Reserved
3TX_DESC_TIMEOUTRW1C0x0NOT IMPLEMENTED. Pending Read was NACK’ed, because the `TX_DESC_STAT` event was not handled in time. Clear: write 1 to this bit in INTERRUPT_STATUS (no hardware auto-clear).
2RX_DESC_TIMEOUTRW1C0x0NOT IMPLEMENTED. Pending Write was NACK’ed, because the `RX_DESC_STAT` event was not handled in time. Clear: write 1 to this bit in INTERRUPT_STATUS (no hardware auto-clear).
1TX_DESC_STATRW1C0x0There is a pending Read Transaction on the I3C Bus. Software should write data to the TX Descriptor Queue and the TX Data Queue. Clear: write 1 to this bit in INTERRUPT_STATUS (no hardware auto-clear — writing to the TX queues does not clear it).
0RX_DESC_STATRW1C0x0There is a pending Write Transaction. Software should read data from the RX Descriptor Queue and the RX Data Queue. Clear: auto-cleared by hardware when software reads the RX Descriptor Queue; writing 1 to this bit in INTERRUPT_STATUS also clears it.

i3c_csr[6].I3C_EC.TTI.INTERRUPT_ENABLE

Table 90. oca_i3c_wrap.i3c_csr[6].I3C_EC.TTI.INTERRUPT_ENABLE fields
BitsFieldAccessResetDescription
31TRANSFER_ERR_STAT_ENRW0x0Enables the corresponding interrupt bit `TRANSFER_ERR_STAT`
30:27Reserved--Reserved
26TX_DESC_COMPLETE_ENRW0x0Enables the corresponding interrupt bit `TX_DESC_COMPLETE_EN`
25TRANSFER_ABORT_STAT_ENRW0x0Enables the corresponding interrupt bit `TRANSFER_ABORT_STAT`
24:14Reserved--Reserved
13IBI_DONE_ENRW0x0Enables the corresponding interrupt bit `IBI_DONE`
12IBI_THLD_STAT_ENRW0x0Enables the corresponding interrupt bit `TTI_IBI_THLD_STAT`
11RX_DESC_THLD_STAT_ENRW0x0Enables the corresponding interrupt bit `TTI_RX_DESC_THLD_STAT`
10TX_DESC_THLD_STAT_ENRW0x0Enables the corresponding interrupt bit `TTI_TX_DESC_THLD_STAT`
9RX_DATA_THLD_STAT_ENRW0x0Enables the corresponding interrupt bit `TTI_RX_DATA_THLD_STAT`
8TX_DATA_THLD_STAT_ENRW0x0Enables the corresponding interrupt bit `TTI_TX_DATA_THLD_STAT`
7:4Reserved--Reserved
3TX_DESC_TIMEOUT_ENRW0x0Enables the corresponding interrupt bit `TX_DESC_TIMEOUT_EN`
2RX_DESC_TIMEOUT_ENRW0x0Enables the corresponding interrupt bit `RX_DESC_TIMEOUT_EN`
1TX_DESC_STAT_ENRW0x0Enables the corresponding interrupt bit `TX_DESC_STAT_EN`
0RX_DESC_STAT_ENRW0x0Enables the corresponding interrupt bit `RX_DESC_STAT_EN`

i3c_csr[6].I3C_EC.TTI.INTERRUPT_FORCE

Table 91. oca_i3c_wrap.i3c_csr[6].I3C_EC.TTI.INTERRUPT_FORCE fields
BitsFieldAccessResetDescription
31TRANSFER_ERR_STAT_FORCERW0x0Enables the corresponding interrupt bit `TRANSFER_ERR_STAT_FORCE`
30:27Reserved--Reserved
26TX_DESC_COMPLETE_FORCERW0x0Enables the corresponding interrupt bit `TX_DESC_COMPLETE_FORCE`
25TRANSFER_ABORT_STAT_FORCERW0x0Enables the corresponding interrupt bit `TRANSFER_ABORT_STAT_FORCE`
24:14Reserved--Reserved
13IBI_DONE_FORCERW0x0Enables the corresponding interrupt bit `IBI_DONE_FORCE`
12IBI_THLD_FORCERW0x0Forces the corresponding interrupt bit `TTI_IBI_THLD_STAT` to be set to 1
11RX_DESC_THLD_FORCERW0x0Forces the corresponding interrupt bit `TTI_RX_DESC_THLD_STAT` to be set to `1`
10TX_DESC_THLD_FORCERW0x0Forces the corresponding interrupt bit `TTI_TX_DESC_THLD_STAT` to be set to `1`
9RX_DATA_THLD_FORCERW0x0Forces the corresponding interrupt bit `TTI_RX_DATA_THLD_STAT` to be set to `1`
8TX_DATA_THLD_FORCERW0x0Forces the corresponding interrupt bit `TTI_TX_DATA_THLD_STAT` to be set to `1`
7:4Reserved--Reserved
3TX_DESC_TIMEOUT_FORCERW0x0Enables the corresponding interrupt bit `TX_DESC_TIMEOUT_FORCE`
2RX_DESC_TIMEOUT_FORCERW0x0Enables the corresponding interrupt bit `RX_DESC_TIMEOUT_FORCE`
1TX_DESC_STAT_FORCERW0x0Enables the corresponding interrupt bit `TX_DESC_STAT_FORCE`
0RX_DESC_STAT_FORCERW0x0Enables the corresponding interrupt bit `RX_DESC_STAT_FORCE`

i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CTRL

Table 92. oca_i3c_wrap.i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CTRL fields
BitsFieldAccessResetDescription
31:13Reserved--Reserved
12RI_INDIRECT_FIFO_OVERFLOW_ERR_DET_ENRW0x1Enable Recovery Interface INDIRECT FIFO overflow error detection and transition to Error state. Set to 0 to disable (overflow is still recorded in interrupt status).
11RI_RX_FIFO_OVERFLOW_ERR_DET_ENRW0x1Enable Recovery Interface RX FIFO overflow error detection and transition to Error state. Set to 0 to disable (overflow is still recorded in interrupt status).
10RI_UNSUPPORTED_ERR_DET_ENRW0x1Enable Recovery Interface unsupported command error detection. Set to 0 to disable.
9RI_READONLY_ERR_DET_ENRW0x1Enable Recovery Interface write-to-read-only error detection. Set to 0 to disable.
8RI_LENGTH_ERR_DET_ENRW0x1Enable Recovery Interface length error detection. Set to 0 to disable.
7RI_PEC_ERR_DET_ENRW0x1Enable Recovery Interface PEC/CRC error detection. Set to 0 to disable.
6FRAMING_ERR_DET_ENRW0x1Enable framing error detection. Set to 0 to disable.
5TE5_ERR_DET_ENRW0x1Enable TE5 error detection. Set to 0 to disable.
4TE4_ERR_DET_ENRW0x1Enable TE4 error detection. Set to 0 to disable.
3TE3_ERR_DET_ENRW0x1Enable TE3 error detection. Set to 0 to disable.
2TE2_ERR_DET_ENRW0x1Enable TE2 error detection. Set to 0 to disable.
1TE1_ERR_DET_ENRW0x1Enable TE1 error detection. Set to 0 to disable.
0TE0_ERR_DET_ENRW0x1Enable TE0 error detection. Set to 0 to disable.

i3c_csr[6].I3C_EC.TTI.TARGET_ERR_INTR_STATUS

Table 93. oca_i3c_wrap.i3c_csr[6].I3C_EC.TTI.TARGET_ERR_INTR_STATUS fields
BitsFieldAccessResetDescription
31:14Reserved--Reserved
13RI_INDIRECT_FIFO_OVERFLOW_ERR_STATRW1C0x0Recovery Interface INDIRECT FIFO overflow error detected
12RI_RX_FIFO_OVERFLOW_ERR_STATRW1C0x0Recovery Interface RX FIFO overflow error detected
11RI_UNSUPPORTED_ERR_STATRW1C0x0Recovery Interface unsupported command error detected
10RI_READONLY_ERR_STATRW1C0x0Recovery Interface write-to-read-only error detected
9RI_LENGTH_ERR_STATRW1C0x0Recovery Interface length mismatch error detected
8RI_PEC_ERR_STATRW1C0x0Recovery Interface PEC/CRC error detected
7FRAMING_ERR_STATRW1C0x0DA padding error (Bit[0] != 0 in SETDASA/SETNEWDA)
6TE5_ERR_STATRW1C0x0TE5: Broadcast/Direct CCC wrong R/W direction
5TE4_ERR_STATRW1C0x0TE4: ENTDAA BCR/DCR mismatch
4TE3_ERR_STATRW1C0x0TE3: ENTDAA PID mismatch
3TE2_ERR_STATRW1C0x0TE2: CCC or Private Write data parity error
2TE1_ERR_STATRW1C0x0TE1: CCC command parity error
1TE0_ERR_STATRW1C0x0TE0: Invalid reserved address + RnW combination
0Reserved--Reserved

i3c_csr[6].I3C_EC.TTI.TARGET_ERR_INTR_ENABLE

Table 94. oca_i3c_wrap.i3c_csr[6].I3C_EC.TTI.TARGET_ERR_INTR_ENABLE fields
BitsFieldAccessResetDescription
31:14Reserved--Reserved
13RI_INDIRECT_FIFO_OVERFLOW_ERR_ENRW0x0Enables the corresponding interrupt bit `RI_INDIRECT_FIFO_OVERFLOW_ERR_STAT`
12RI_RX_FIFO_OVERFLOW_ERR_ENRW0x0Enables the corresponding interrupt bit `RI_RX_FIFO_OVERFLOW_ERR_STAT`
11RI_UNSUPPORTED_ERR_ENRW0x0Enables the corresponding interrupt bit `RI_UNSUPPORTED_ERR_STAT`
10RI_READONLY_ERR_ENRW0x0Enables the corresponding interrupt bit `RI_READONLY_ERR_STAT`
9RI_LENGTH_ERR_ENRW0x0Enables the corresponding interrupt bit `RI_LENGTH_ERR_STAT`
8RI_PEC_ERR_ENRW0x0Enables the corresponding interrupt bit `RI_PEC_ERR_STAT`
7FRAMING_ERR_ENRW0x0Enables the corresponding interrupt bit `FRAMING_ERR_STAT`
6TE5_ERR_ENRW0x0Enables the corresponding interrupt bit `TE5_ERR_STAT`
5TE4_ERR_ENRW0x0Enables the corresponding interrupt bit `TE4_ERR_STAT`
4TE3_ERR_ENRW0x0Enables the corresponding interrupt bit `TE3_ERR_STAT`
3TE2_ERR_ENRW0x0Enables the corresponding interrupt bit `TE2_ERR_STAT`
2TE1_ERR_ENRW0x0Enables the corresponding interrupt bit `TE1_ERR_STAT`
1TE0_ERR_ENRW0x0Enables the corresponding interrupt bit `TE0_ERR_STAT`
0Reserved--Reserved

i3c_csr[6].I3C_EC.TTI.TARGET_ERR_INTR_FORCE

Table 95. oca_i3c_wrap.i3c_csr[6].I3C_EC.TTI.TARGET_ERR_INTR_FORCE fields
BitsFieldAccessResetDescription
31:14Reserved--Reserved
13RI_INDIRECT_FIFO_OVERFLOW_ERR_FORCERW0x0Forces the corresponding interrupt bit `RI_INDIRECT_FIFO_OVERFLOW_ERR_STAT` to be set to 1
12RI_RX_FIFO_OVERFLOW_ERR_FORCERW0x0Forces the corresponding interrupt bit `RI_RX_FIFO_OVERFLOW_ERR_STAT` to be set to 1
11RI_UNSUPPORTED_ERR_FORCERW0x0Forces the corresponding interrupt bit `RI_UNSUPPORTED_ERR_STAT` to be set to 1
10RI_READONLY_ERR_FORCERW0x0Forces the corresponding interrupt bit `RI_READONLY_ERR_STAT` to be set to 1
9RI_LENGTH_ERR_FORCERW0x0Forces the corresponding interrupt bit `RI_LENGTH_ERR_STAT` to be set to 1
8RI_PEC_ERR_FORCERW0x0Forces the corresponding interrupt bit `RI_PEC_ERR_STAT` to be set to 1
7FRAMING_ERR_FORCERW0x0Forces the corresponding interrupt bit `FRAMING_ERR_STAT` to be set to 1
6TE5_ERR_FORCERW0x0Forces the corresponding interrupt bit `TE5_ERR_STAT` to be set to 1
5TE4_ERR_FORCERW0x0Forces the corresponding interrupt bit `TE4_ERR_STAT` to be set to 1
4TE3_ERR_FORCERW0x0Forces the corresponding interrupt bit `TE3_ERR_STAT` to be set to 1
3TE2_ERR_FORCERW0x0Forces the corresponding interrupt bit `TE2_ERR_STAT` to be set to 1
2TE1_ERR_FORCERW0x0Forces the corresponding interrupt bit `TE1_ERR_STAT` to be set to 1
1TE0_ERR_FORCERW0x0Forces the corresponding interrupt bit `TE0_ERR_STAT` to be set to 1
0Reserved--Reserved

i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_TE0

Table 96. oca_i3c_wrap.i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_TE0 fields
BitsFieldAccessResetDescription
31:8Reserved--Reserved
7:0CNTRW0x0Error count (saturates at 255). Write 0 to clear.

i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_TE1

Table 97. oca_i3c_wrap.i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_TE1 fields
BitsFieldAccessResetDescription
31:8Reserved--Reserved
7:0CNTRW0x0Error count (saturates at 255). Write 0 to clear.

i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_TE2

Table 98. oca_i3c_wrap.i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_TE2 fields
BitsFieldAccessResetDescription
31:8Reserved--Reserved
7:0CNTRW0x0Error count (saturates at 255). Write 0 to clear.

i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_TE3

Table 99. oca_i3c_wrap.i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_TE3 fields
BitsFieldAccessResetDescription
31:8Reserved--Reserved
7:0CNTRW0x0Error count (saturates at 255). Write 0 to clear.

i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_TE4

Table 100. oca_i3c_wrap.i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_TE4 fields
BitsFieldAccessResetDescription
31:8Reserved--Reserved
7:0CNTRW0x0Error count (saturates at 255). Write 0 to clear.

i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_TE5

Table 101. oca_i3c_wrap.i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_TE5 fields
BitsFieldAccessResetDescription
31:8Reserved--Reserved
7:0CNTRW0x0Error count (saturates at 255). Write 0 to clear.

i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_FRAMING

Table 102. oca_i3c_wrap.i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_FRAMING fields
BitsFieldAccessResetDescription
31:8Reserved--Reserved
7:0CNTRW0x0Error count (saturates at 255). Write 0 to clear.

i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_RI_PEC

Table 103. oca_i3c_wrap.i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_RI_PEC fields
BitsFieldAccessResetDescription
31:8Reserved--Reserved
7:0CNTRW0x0Error count (saturates at 255). Write 0 to clear.

i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_RI_LENGTH

Table 104. oca_i3c_wrap.i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_RI_LENGTH fields
BitsFieldAccessResetDescription
31:8Reserved--Reserved
7:0CNTRW0x0Error count (saturates at 255). Write 0 to clear.

i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_RI_READONLY

Table 105. oca_i3c_wrap.i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_RI_READONLY fields
BitsFieldAccessResetDescription
31:8Reserved--Reserved
7:0CNTRW0x0Error count (saturates at 255). Write 0 to clear.

i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_RI_UNSUPPORTED

Table 106. oca_i3c_wrap.i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_RI_UNSUPPORTED fields
BitsFieldAccessResetDescription
31:8Reserved--Reserved
7:0CNTRW0x0Error count (saturates at 255). Write 0 to clear.

i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_RI_RX_FIFO_OVERFLOW

Table 107. oca_i3c_wrap.i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_RI_RX_FIFO_OVERFLOW fields
BitsFieldAccessResetDescription
31:8Reserved--Reserved
7:0CNTRW0x0Error count (saturates at 255). Write 0 to clear.

i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_RI_INDIRECT_FIFO_OVERFLOW

Table 108. oca_i3c_wrap.i3c_csr[6].I3C_EC.TTI.TARGET_ERR_CNT_RI_INDIRECT_FIFO_OVERFLOW fields
BitsFieldAccessResetDescription
31:8Reserved--Reserved
7:0CNTRW0x0Error count (saturates at 255). Write 0 to clear.

i3c_csr[6].I3C_EC.TTI.RX_DESC_QUEUE_PORT

Table 109. oca_i3c_wrap.i3c_csr[6].I3C_EC.TTI.RX_DESC_QUEUE_PORT fields
BitsFieldAccessResetDescription
31:0RX_DESCR0x0RX Data

i3c_csr[6].I3C_EC.TTI.RX_DATA_PORT

Table 110. oca_i3c_wrap.i3c_csr[6].I3C_EC.TTI.RX_DATA_PORT fields
BitsFieldAccessResetDescription
31:0RX_DATAR0x0RX Data

i3c_csr[6].I3C_EC.TTI.TX_DESC_QUEUE_PORT

Table 111. oca_i3c_wrap.i3c_csr[6].I3C_EC.TTI.TX_DESC_QUEUE_PORT fields
BitsFieldAccessResetDescription
31:0TX_DESCW0x0TX Data

i3c_csr[6].I3C_EC.TTI.TX_DATA_PORT

Table 112. oca_i3c_wrap.i3c_csr[6].I3C_EC.TTI.TX_DATA_PORT fields
BitsFieldAccessResetDescription
31:0TX_DATAW0x0TX Data

i3c_csr[6].I3C_EC.TTI.IBI_PORT

Table 113. oca_i3c_wrap.i3c_csr[6].I3C_EC.TTI.IBI_PORT fields
BitsFieldAccessResetDescription
31:0IBI_DATAW0x0IBI Data

i3c_csr[6].I3C_EC.TTI.QUEUE_SIZE

Table 114. oca_i3c_wrap.i3c_csr[6].I3C_EC.TTI.QUEUE_SIZE fields
BitsFieldAccessResetDescription
31:24TX_DATA_BUFFER_SIZER0x5Transmit Data Buffer Size in DWORDs calculated as `2^(N+1)`
23:16RX_DATA_BUFFER_SIZER0x5Receive Data Buffer Size in DWORDs calculated as `2^(N+1)`
15:8TX_DESC_BUFFER_SIZER0x4TX Descriptor Buffer Size in DWORDs calculated as `2^(N+1)`
7:0RX_DESC_BUFFER_SIZER0x4RX Descriptor Buffer Size in DWORDs calculated as `2^(N+1)`

i3c_csr[6].I3C_EC.TTI.IBI_QUEUE_SIZE

Table 115. oca_i3c_wrap.i3c_csr[6].I3C_EC.TTI.IBI_QUEUE_SIZE fields
BitsFieldAccessResetDescription
31:8Reserved--Reserved
7:0IBI_QUEUE_SIZER0x4IBI Queue Size in DWORDs calculated as `2^(N+1)`

i3c_csr[6].I3C_EC.TTI.QUEUE_THLD_CTRL

Table 116. oca_i3c_wrap.i3c_csr[6].I3C_EC.TTI.QUEUE_THLD_CTRL fields
BitsFieldAccessResetDescription
31:24IBI_THLDRW0x1Controls the minimum number of IBI Queue entries needed to trigger the IBI threshold interrupt.
23:16Reserved--Reserved
15:8RX_DESC_THLDRW0x1Controls the minimum number of TTI RX Descriptor Queue entries needed to trigger the TTI RX Descriptor interrupt.
7:0TX_DESC_THLDRW0x1Controls the minimum number of empty TTI TX Descriptor Queue entries needed to trigger the TTI TX Descriptor interrupt.

i3c_csr[6].I3C_EC.TTI.DATA_BUFFER_THLD_CTRL

Table 117. oca_i3c_wrap.i3c_csr[6].I3C_EC.TTI.DATA_BUFFER_THLD_CTRL fields
BitsFieldAccessResetDescription
31:27Reserved--Reserved
26:24RX_START_THLDRW0x1Minimum number of TTI RX Data queue entries of data received, in DWORDs, that will trigger the TTI RX Data interrupt. Interrupt triggers when `2^(N+1)` RX Buffer DWORD entries are received during the Read transfer.
23:19Reserved--Reserved
18:16TX_START_THLDRW0x1Minimum number of available TTI TX Data queue entries, in DWORDs, that will trigger the TTI TX Data interrupt. Interrupt triggers when `2^(N+1)` TX Buffer DWORD entries are available.
15:11Reserved--Reserved
10:8RX_DATA_THLDRW0x1Minimum number of TTI RX Data queue entries of data received, in DWORDs, that will trigger the TTI RX Data interrupt. Interrupt triggers when `2^(N+1)` RX Buffer DWORD entries are received during the Read transfer.
7:3Reserved--Reserved
2:0TX_DATA_THLDRW0x1Minimum number of available TTI TX Data queue entries, in DWORDs, that will trigger the TTI TX Data interrupt. Interrupt triggers when `2^(N+1)` TX Buffer DWORD entries are available.

i3c_csr[6].I3C_EC.SoCMgmtIf.EXTCAP_HEADER

Table 118. oca_i3c_wrap.i3c_csr[6].I3C_EC.SoCMgmtIf.EXTCAP_HEADER fields
BitsFieldAccessResetDescription
31:24Reserved--Reserved
23:8CAP_LENGTHR0x1ACapability Structure Length in DWORDs
7:0CAP_IDR0xC1Extended Capability ID

i3c_csr[6].I3C_EC.SoCMgmtIf.SOC_MGMT_CONTROL

Table 119. oca_i3c_wrap.i3c_csr[6].I3C_EC.SoCMgmtIf.SOC_MGMT_CONTROL fields
BitsFieldAccessResetDescription
31:0PLACEHOLDERRW0x0-

i3c_csr[6].I3C_EC.SoCMgmtIf.SOC_MGMT_STATUS

Table 120. oca_i3c_wrap.i3c_csr[6].I3C_EC.SoCMgmtIf.SOC_MGMT_STATUS fields
BitsFieldAccessResetDescription
31:0PLACEHOLDERRW0x0-

i3c_csr[6].I3C_EC.SoCMgmtIf.REC_INTF_CFG

Table 121. oca_i3c_wrap.i3c_csr[6].I3C_EC.SoCMgmtIf.REC_INTF_CFG fields
BitsFieldAccessResetDescription
31:2Reserved--Reserved
1REC_PAYLOAD_DONERW0x0Inform Recovery Handler that payload transfer is finished.
0REC_INTF_BYPASSRW0x0Choose Recovery Interface access type:

* 0 - I3C Core

* 1 - direct AXI

i3c_csr[6].I3C_EC.SoCMgmtIf.REC_INTF_REG_W1C_ACCESS

Table 122. oca_i3c_wrap.i3c_csr[6].I3C_EC.SoCMgmtIf.REC_INTF_REG_W1C_ACCESS fields
BitsFieldAccessResetDescription
31:24Reserved--Reserved
23:16INDIRECT_FIFO_CTRL_RESETRW0x0Write to 'Indirect memory configuration - reset' register, mocking a hardware access (bypassing 'write 1 to clear' register property).
15:8RECOVERY_CTRL_ACTIVATE_REC_IMGRW0x0Write to 'Recovery Control - Activate Recovery Image' register, mocking a hardware access (bypassing 'write 1 to clear' register property).
7:0DEVICE_RESET_CTRLRW0x0Write to 'Reset control - Device Reset Control' register, mocking a hardware access (bypassing 'write 1 to clear' register property).

i3c_csr[6].I3C_EC.SoCMgmtIf.SOC_MGMT_RSVD_2

Table 123. oca_i3c_wrap.i3c_csr[6].I3C_EC.SoCMgmtIf.SOC_MGMT_RSVD_2 fields
BitsFieldAccessResetDescription
31:0PLACEHOLDERRW0x0-

i3c_csr[6].I3C_EC.SoCMgmtIf.SOC_MGMT_RSVD_3

Table 124. oca_i3c_wrap.i3c_csr[6].I3C_EC.SoCMgmtIf.SOC_MGMT_RSVD_3 fields
BitsFieldAccessResetDescription
31:0PLACEHOLDERRW0x0-

i3c_csr[6].I3C_EC.SoCMgmtIf.SOC_PAD_CONF

Table 125. oca_i3c_wrap.i3c_csr[6].I3C_EC.SoCMgmtIf.SOC_PAD_CONF fields
BitsFieldAccessResetDescription
31:24PAD_TYPERW0x1Select pad type

0 - Bidirectional

1 - Open-drain

2 - Input-only

3 - Analog input
23:8Reserved--Reserved
7VIRTUAL_OD_ENRW0x0Enable virtual open drain:

0 - disabled

1 - enabled
6OD_ENRW0x0Enable Open-Drain:

0 - disabled

1 - enabled
5IO_INVERSIONRW0x0Invert I/O signal:

0 - signals pass-through

1 - signals are inverted
4PULL_ENRW0x0Enable Pull:

0 - disabled

1 - enabled
3PULL_DIRRW0x0Direction of the pull:

0 - Pull down

1 - Pull up
2KEEPER_ENRW0x0Enable the High-Keeper:

0 - disabled

1 - enabled
1SCHMITT_ENRW0x0Enable the Schmitt Trigger:

0 - disabled

1 - enabled
0INPUT_ENABLERW0x1Enable input:

0 - enabled

1 - disabled

i3c_csr[6].I3C_EC.SoCMgmtIf.SOC_PAD_ATTR

Table 126. oca_i3c_wrap.i3c_csr[6].I3C_EC.SoCMgmtIf.SOC_PAD_ATTR fields
BitsFieldAccessResetDescription
31:24DRIVE_STRENGTHRW0xFSelect driver strength

'0 - lowest

'1 - highest
23:16Reserved--Reserved
15:8DRIVE_SLEW_RATERW0xFSelect driver slew rate

'0 - lowest

'1 - highest
7:0Reserved--Reserved

i3c_csr[6].I3C_EC.SoCMgmtIf.SOC_MGMT_FEATURE_2

Table 127. oca_i3c_wrap.i3c_csr[6].I3C_EC.SoCMgmtIf.SOC_MGMT_FEATURE_2 fields
BitsFieldAccessResetDescription
31:0PLACEHOLDERRW0x0Reserved for: I/O ring and pad configuration

i3c_csr[6].I3C_EC.SoCMgmtIf.SOC_MGMT_FEATURE_3

Table 128. oca_i3c_wrap.i3c_csr[6].I3C_EC.SoCMgmtIf.SOC_MGMT_FEATURE_3 fields
BitsFieldAccessResetDescription
31:0PLACEHOLDERRW0x0Reserved for: I/O ring and pad configuration

i3c_csr[6].I3C_EC.SoCMgmtIf.T_R_REG

Table 129. oca_i3c_wrap.i3c_csr[6].I3C_EC.SoCMgmtIf.T_R_REG fields
BitsFieldAccessResetDescription
31:20Reserved--Reserved
19:0T_RRW0x0Rise time of both SDA and SCL in clock units

i3c_csr[6].I3C_EC.SoCMgmtIf.T_F_REG

Table 130. oca_i3c_wrap.i3c_csr[6].I3C_EC.SoCMgmtIf.T_F_REG fields
BitsFieldAccessResetDescription
31:20Reserved--Reserved
19:0T_FRW0x0Fall time of both SDA and SCL in clock units

i3c_csr[6].I3C_EC.SoCMgmtIf.T_SU_DAT_REG

Table 131. oca_i3c_wrap.i3c_csr[6].I3C_EC.SoCMgmtIf.T_SU_DAT_REG fields
BitsFieldAccessResetDescription
31:20Reserved--Reserved
19:0T_SU_DATRW0x0Data setup time in clock units

i3c_csr[6].I3C_EC.SoCMgmtIf.T_SU_DAT_I2C_REG

Table 132. oca_i3c_wrap.i3c_csr[6].I3C_EC.SoCMgmtIf.T_SU_DAT_I2C_REG fields
BitsFieldAccessResetDescription
31:20Reserved--Reserved
19:0T_SU_DAT_I2CRW0x0Data setup time in I2C mode in clock units

i3c_csr[6].I3C_EC.SoCMgmtIf.T_HD_DAT_REG

Table 133. oca_i3c_wrap.i3c_csr[6].I3C_EC.SoCMgmtIf.T_HD_DAT_REG fields
BitsFieldAccessResetDescription
31:20Reserved--Reserved
19:0T_HD_DATRW0x0Data hold time in clock units

i3c_csr[6].I3C_EC.SoCMgmtIf.T_HIGH_REG

Table 134. oca_i3c_wrap.i3c_csr[6].I3C_EC.SoCMgmtIf.T_HIGH_REG fields
BitsFieldAccessResetDescription
31:20Reserved--Reserved
19:0T_HIGHRW0x0-

i3c_csr[6].I3C_EC.SoCMgmtIf.T_HIGH_OD_REG

Table 135. oca_i3c_wrap.i3c_csr[6].I3C_EC.SoCMgmtIf.T_HIGH_OD_REG fields
BitsFieldAccessResetDescription
31:20Reserved--Reserved
19:0T_HIGH_ODRW0x0-

i3c_csr[6].I3C_EC.SoCMgmtIf.T_HIGH_INIT_OD_REG

Table 136. oca_i3c_wrap.i3c_csr[6].I3C_EC.SoCMgmtIf.T_HIGH_INIT_OD_REG fields
BitsFieldAccessResetDescription
31:20Reserved--Reserved
19:0T_HIGH_INIT_ODRW0x0-

i3c_csr[6].I3C_EC.SoCMgmtIf.T_HIGH_I2C_REG

Table 137. oca_i3c_wrap.i3c_csr[6].I3C_EC.SoCMgmtIf.T_HIGH_I2C_REG fields
BitsFieldAccessResetDescription
31:20Reserved--Reserved
19:0T_HIGH_I2CRW0x0-

i3c_csr[6].I3C_EC.SoCMgmtIf.T_LOW_REG

Table 138. oca_i3c_wrap.i3c_csr[6].I3C_EC.SoCMgmtIf.T_LOW_REG fields
BitsFieldAccessResetDescription
31:20Reserved--Reserved
19:0T_LOWRW0x0Low period of the SCL in clock units

i3c_csr[6].I3C_EC.SoCMgmtIf.T_LOW_OD_REG

Table 139. oca_i3c_wrap.i3c_csr[6].I3C_EC.SoCMgmtIf.T_LOW_OD_REG fields
BitsFieldAccessResetDescription
31:20Reserved--Reserved
19:0T_LOW_ODRW0x0Low period of the SCL in Open-Drain mode in clock units

i3c_csr[6].I3C_EC.SoCMgmtIf.T_LOW_I2C_REG

Table 140. oca_i3c_wrap.i3c_csr[6].I3C_EC.SoCMgmtIf.T_LOW_I2C_REG fields
BitsFieldAccessResetDescription
31:20Reserved--Reserved
19:0T_LOW_I2CRW0x0Low period of the SCL in I2C mode in clock units

i3c_csr[6].I3C_EC.SoCMgmtIf.T_HD_STA_REG

Table 141. oca_i3c_wrap.i3c_csr[6].I3C_EC.SoCMgmtIf.T_HD_STA_REG fields
BitsFieldAccessResetDescription
31:20Reserved--Reserved
19:0T_HD_STARW0x0Hold time for START in clock units

i3c_csr[6].I3C_EC.SoCMgmtIf.T_HD_STA_I2C_REG

Table 142. oca_i3c_wrap.i3c_csr[6].I3C_EC.SoCMgmtIf.T_HD_STA_I2C_REG fields
BitsFieldAccessResetDescription
31:20Reserved--Reserved
19:0T_HD_STA_I2CRW0x0Hold time for START in I2C mode in clock units

i3c_csr[6].I3C_EC.SoCMgmtIf.T_HD_RSTA_REG

Table 143. oca_i3c_wrap.i3c_csr[6].I3C_EC.SoCMgmtIf.T_HD_RSTA_REG fields
BitsFieldAccessResetDescription
31:20Reserved--Reserved
19:0T_HD_RSTARW0x0Hold time for repeated START in clock units

i3c_csr[6].I3C_EC.SoCMgmtIf.T_SU_STA_REG

Table 144. oca_i3c_wrap.i3c_csr[6].I3C_EC.SoCMgmtIf.T_SU_STA_REG fields
BitsFieldAccessResetDescription
31:20Reserved--Reserved
19:0T_SU_STARW0x0Setup time for repeated START in clock units

i3c_csr[6].I3C_EC.SoCMgmtIf.T_SU_STA_I2C_REG

Table 145. oca_i3c_wrap.i3c_csr[6].I3C_EC.SoCMgmtIf.T_SU_STA_I2C_REG fields
BitsFieldAccessResetDescription
31:20Reserved--Reserved
19:0T_SU_STA_I2CRW0x0Setup time for repeated START in I2C mode in clock units

i3c_csr[6].I3C_EC.SoCMgmtIf.T_SU_STO_REG

Table 146. oca_i3c_wrap.i3c_csr[6].I3C_EC.SoCMgmtIf.T_SU_STO_REG fields
BitsFieldAccessResetDescription
31:20Reserved--Reserved
19:0T_SU_STORW0x0Setup time for STOP in clock units

i3c_csr[6].I3C_EC.SoCMgmtIf.T_SU_STO_I2C_REG

Table 147. oca_i3c_wrap.i3c_csr[6].I3C_EC.SoCMgmtIf.T_SU_STO_I2C_REG fields
BitsFieldAccessResetDescription
31:20Reserved--Reserved
19:0T_SU_STO_I2CRW0x0Setup time for STOP in in I2C mode clock units

i3c_csr[6].I3C_EC.SoCMgmtIf.T_DS_OD_REG

Table 148. oca_i3c_wrap.i3c_csr[6].I3C_EC.SoCMgmtIf.T_DS_OD_REG fields
BitsFieldAccessResetDescription
31:20Reserved--Reserved
19:0T_DS_ODRW0x0Setup time for SDA during START in clock units

i3c_csr[6].I3C_EC.SoCMgmtIf.T_FREE_REG

Table 149. oca_i3c_wrap.i3c_csr[6].I3C_EC.SoCMgmtIf.T_FREE_REG fields
BitsFieldAccessResetDescription
31:0T_FREERW0xCBus Free Time Between a STOP and a START

i3c_csr[6].I3C_EC.SoCMgmtIf.T_FREE_I2C_REG

Table 150. oca_i3c_wrap.i3c_csr[6].I3C_EC.SoCMgmtIf.T_FREE_I2C_REG fields
BitsFieldAccessResetDescription
31:0T_FREE_I2CRW0xCBus Free Time Between a STOP and a START in I2C mode

i3c_csr[6].I3C_EC.SoCMgmtIf.T_AVAL_REG

Table 151. oca_i3c_wrap.i3c_csr[6].I3C_EC.SoCMgmtIf.T_AVAL_REG fields
BitsFieldAccessResetDescription
31:0T_AVALRW0x12C-

i3c_csr[6].I3C_EC.SoCMgmtIf.T_IDLE_REG

Table 152. oca_i3c_wrap.i3c_csr[6].I3C_EC.SoCMgmtIf.T_IDLE_REG fields
BitsFieldAccessResetDescription
31:0T_IDLERW0xEA60Time in clock cycles from STOP detection until Bus Idle Condition (tIDLE). Configure based on System Clock

i3c_csr[6].I3C_EC.SoCMgmtIf.HDR_TIMEOUT_EN_REG

Table 153. oca_i3c_wrap.i3c_csr[6].I3C_EC.SoCMgmtIf.HDR_TIMEOUT_EN_REG fields
BitsFieldAccessResetDescription
31:1Reserved--Reserved
0HDR_TIMEOUT_ENRW0x0Enable bit for the optional 60us HDR error recovery timer (I3C spec 5.1.10.1.9). When enabled, the Target can recover from TE0/TE1 errors if both SCL and SDA stay High for a period exceeding the configured threshold. Disabled on reset.

i3c_csr[6].I3C_EC.SoCMgmtIf.T_HDR_TIMEOUT_REG

Table 154. oca_i3c_wrap.i3c_csr[6].I3C_EC.SoCMgmtIf.T_HDR_TIMEOUT_REG fields
BitsFieldAccessResetDescription
31:20Reserved--Reserved
19:0T_HDR_TIMEOUTRW0xEA60Timer threshold in clock cycles for the optional HDR error recovery (I3C spec 5.1.10.1.9). If both SCL and SDA stay High for this many clock cycles during a TE0/TE1 error-induced HDR mode, the Target exits HDR mode and returns to Idle. Configure based on System Clock to achieve 60us.

i3c_csr[6].I3C_EC.CtrlCfg.EXTCAP_HEADER

Table 155. oca_i3c_wrap.i3c_csr[6].I3C_EC.CtrlCfg.EXTCAP_HEADER fields
BitsFieldAccessResetDescription
31:24Reserved--Reserved
23:8CAP_LENGTHR0x2Capability Structure Length in DWORDs
7:0CAP_IDR0x2Extended Capability ID

i3c_csr[6].I3C_EC.CtrlCfg.CONTROLLER_CONFIG

Table 156. oca_i3c_wrap.i3c_csr[6].I3C_EC.CtrlCfg.CONTROLLER_CONFIG fields
BitsFieldAccessResetDescription
31:6Reserved--Reserved
5:4OPERATION_MODER0x1-
3:0Reserved--Reserved

i3c_csr[6].I3C_EC.TERMINATION_EXTCAP_HEADER

Table 157. oca_i3c_wrap.i3c_csr[6].I3C_EC.TERMINATION_EXTCAP_HEADER fields
BitsFieldAccessResetDescription
31:24Reserved--Reserved
23:8CAP_LENGTHR0x1Capability Structure Length in DWORDs
7:0CAP_IDR0x0Extended Capability ID

i3c_csr[6].DAT.DAT_MEMORY[128]

Table 158. oca_i3c_wrap.i3c_csr[6].DAT.DAT_MEMORY[128] fields
BitsFieldAccessResetDescription
63:59Reserved--Reserved
58:51AUTOCMD_HDR_CODERW-Device auto command in HDR mode
50:48AUTOCMD_MODERW-Auto command mode and speed
47:40AUTOCMD_VALUERW-IBI value that triggers auto command
39:32AUTOCMD_MASKRW-IBI mask
31DEVICERW-Device type:
0 - I3C device,
1 - I2C device.
30:29DEV_NACK_RETRY_CNTRW-Number of retries before giving up
28:26RING_IDRW-Send IBI read to ring bundle
25:24Reserved--Reserved
23:16DYNAMIC_ADDRESSRW-I3C dynamic address
15TSRW-Enable/disable IBI timestamp
14CRR_REJECTRW-Reject device's request for controller change
13IBI_REJECTRW-Reject device's request for IBI
12IBI_PAYLOADRW-Device's IBI contains data payload
11:7Reserved--Reserved
6:0STATIC_ADDRESSRW-I3C/I2C static device address

i3c_csr[6].DCT.DCT_MEMORY[128]

Table 159. oca_i3c_wrap.i3c_csr[6].DCT.DCT_MEMORY[128] fields
BitsFieldAccessResetDescription
127:104Reserved--Reserved
103:96DYNAMIC_ADDRESSR-Device I3C Dynamic Address after ENTDAA
95:80Reserved--Reserved
79:72BCRR-Value of the I3C device's Bus Characteristics Register
71:64DCRR-Value of the I3C device's Device Characteristics Register
63:48Reserved--Reserved
47:32PID_LOR-Device Provisional ID Low
31:0PID_HIR-Device Provisional ID High