JTAG Operation

The DTP instantiates a single JTAG Interface Unit (JIU) as the primary debug entry point for the chiplet. The JIU connects to:

Figure 1 shows the PTAP, secondary scan path, and iJTAG instrument network.

Read Figure 1 along the arrows from TDI to TDO. TDI reaches every register and external chain at once; the IR and TDR mux returns the instruction register in Shift-IR and, in Shift-DR, the register the current instruction selects. Italic labels beside a mux name the instructions or the select bit that choose its input, and 0 or 1 at a mux input is the select value that picks it. The PTAP output then enters the STAP chain, which is scanned only while the TAP_3DCR STAP-select bit is set: the bit gates the chain’s scan strobes and selects its return onto TDO. Otherwise TDO takes the PTAP output directly. TDO is retimed on the falling edge of TCK except during a ZERO_LENGTH_BYPASS DR scan with the STAP-select bit clear, when the last mux takes the TDO mux output ahead of the retimer and TDI reaches TDO combinationally. While the bit is set, ZERO_LENGTH_BYPASS behaves exactly as BYPASS: the PTAP bypass register leads the STAP chain and the chain’s return is retimed. The figure counts the extra STAPs by the jtag_intf_unit parameter NUM_EXTRA_STAPS, which dtp sets from JTAG_NUM_EXTRA_STAPS. Each STAP and SIB carries, in italics, the dbg_disable_i field that closes it. Dashed blocks exist only when their enable parameter is set, as the list below gives for the STAPs; the JTAG2AXI bridges follow JTAG_SMC_DBG_ENABLE and JTAG_SEP_DBG_ENABLE. Each STAP adds one SIB bit to the chain; opening the SIB inserts the STAP’s 3-bit 3DCR, and setting the 3DCR STAP-select bit splices in its secondary TAP. Each iJTAG SIB inserts its external segment after its SIB bit while that bit is set.

The PTAP secondary scan path connects the STAPs in this fixed order:

When a STAP is disabled by parameter, the DTP bypasses it in the secondary scan chain and drives its host outputs low, apart from TCK, which still follows the PTAP.

The PTAP contains three JTAG2AXI bridges, each selected by its own group of six instructions (Table 1). The request and response type parameters of a bridge set its bus type, address width and data width. Its read and write pipeline-depth parameters set how many transactions it queues, where 0 allows a single outstanding transaction. The table lists the DTP defaults. Each bridge reports its configuration in its *_JTAG2AXI_CAPS register. Every output of a bridge’s manager port depends only on the bridge’s internal state, so no combinational path runs from the port’s inputs to its outputs. A bridge accepts a response from the cycle after its request handshake completes.

See Clock Domains.

See Reset Architecture.

See IC_RESET Overrides.

dbg_disable_i (sep_lifecycle_ctrl_pkg::dbg_disable_t) is a per-path debug/test disable vector. Each field is active-high (1 = path disabled). The JTAG interface unit synchronizes the vector into the TCK domain and applies each field to the named path.

Table 2 maps each debug path to its active-high disable field.

A disabled path remains observable only where required for control and readback. For a JTAG2AXI bridge, disabling means TDR update registers are not latched. The disable gates the idle state: an active AXI transaction continues to completion, and buffered requests are flushed when idle is reached. For a STAP, the host-visible scan access is clamped so the disabled path cannot reach downstream secure logic.

The STAP and iJTAG fields are applied in jtag_intf_unit; the three JTAG2AXI fields are applied in jtag_ptap.