OTBN PKA Public Key Accelerator

The module is based on the OpenTitan OTBN design.

Features:

  • Fully programmable big integer processor

    • 256-bit data path with 32 entry register file

    • 32-bit control path with 32 entry register file

    • Complex flow control: conditional branching, loops, call/return with optimized hardware for performance

    • Dual status control bits to assist in big integer computation

    • Optimized modular arithmetic on big integers

  • Access to entropy noise stream from the TRNG

The OTBN is programmed in assembly and its runtime driver library currently supports the following algorithms:

  • ECDSA P256, P384

  • ECDH P256, P384

  • Ed25519

  • X25519

  • RSA 2k, 3k, 4k

    • Key generation, signature generation and signature verification

  • SHA256, SHA-512

Since the OTBN is programmable, more algorithms can easily be developed at a later time. The microcode is loaded into SRAM based instruction memory allowing firmware updates to be made in the field.

OpenTitan OTBN core reference architecture
Figure 1. OpenTitan OTBN core reference architecture

Figure 1 shows the upstream core. The OCAH bus, key-delivery, and entropy connections are described in the integration details below.

1. OCAH Modifications

  • AXI4-lite key bus slave interface replaces side loading interface

  • AXI4-lite control/status bus slave interface

The OTBN host path is the most complex OpenTitan path. The crypto interconnect applies a CACHE_MODIFIABLE bit fix before the axi_dw_converter, because the VeeR CPU may emit non-modifiable cache attributes for MMIO accesses that would be rejected by the AXI-to-AXI-Lite converter. After data-width conversion and AXI-Lite isolation, sep_crypto_otbn_wrapper bridges the request to TL-UL and drives the standard otbn core configured with Stub = 0 and RegFile = RegFileFF.

OTBN’s instruction and data memories are external SRAM macros; the IMEM and DMEM prim_ram_1p_scr ports are brought out of the wrapper to the sep_crypto top level. The two random-number request ports (edn_rnd, edn_urnd) are served over native-protocol EDN by the shared drbg_axis_edn_adapter instance u_axis_edn_crypto_s3c_scan in sep_crypto, which converts the post-CSRNG DRBG AXI-Stream feed assigned to the crypto sink domain into per-client EDN responses. The adapter forwards the per-beat FIPS tag through a generic AXI-Stream tuser sideband. The CSRNG seed tag and external entropy mux tag are tied high by the integration’s provisional policy. A high tag prevents a FIPS-tag failure for that response but does not prove that the entropy is FIPS compliant. The OTP scramble key handshake is tied to fixed values. Life-cycle escalation and RMA request signals are tied to their inactive state. OTBN occupies alert indices [2:1] in OpenTitan Alert Termination and exports a single intr_done_o interrupt.

The Key Manager delivers a 384-bit OTBN key as twelve words per share, the widest delivery in the subsystem, in the format given in Key Manager Key Delivery. OTBN is the only accelerator that does not combine the shares in hardware. The shares are exposed to the executing program through the KEY_S0_L / KEY_S0_H and KEY_S1_L / KEY_S1_H special registers, each share split into a 256-bit low and a 128-bit high half, and the program is responsible for reconstructing the key as the XOR of the two shares. Each share is qualified independently: reading a share whose key is not valid sets ERR_BITS.KEY_INVALID and stops the program rather than returning key material.

Consult the OpenTitan OTBN documentation for the authoritative core functionality of the IP. The Programmer’s Guide gives the programming guidance for this block. The register map follows below.

2. Memory Map and Register Reference

2.1. Memory Map

Register offsets are relative to the block base in the subsystem memory map. The detailed map below defines each register and its fields.

2.2. Detailed Register Map

OpenTitan Big Number Accelerator

Programmable coprocessor for asymmetric cryptography with SCA and FI countermeasures

Register List:

Table 1. OpenTitan Big Number Accelerator register list
AddressNameAccessDescription
0x0INTR_STATERW-
0x4INTR_ENABLERW-
0x8INTR_TESTW-
0xCALERT_TESTW-
0x10CMDW-
0x14CTRLRW-
0x18STATUSR-
0x1CERR_BITSRW-
0x20FATAL_ALERT_CAUSER-
0x24INSN_CNTRW-
0x28LOAD_CHECKSUMRW-

Register Details:

INTR_STATE

Table 2. otbn.INTR_STATE fields
BitsFieldAccessResetDescription
31:1Reserved--Reserved
0doneRW1C0x0OTBN has completed the operation.

INTR_ENABLE

Table 3. otbn.INTR_ENABLE fields
BitsFieldAccessResetDescription
31:1Reserved--Reserved
0doneRW0x0Enable interrupt when !!INTR_STATE.done is set.

INTR_TEST

Table 4. otbn.INTR_TEST fields
BitsFieldAccessResetDescription
31:1Reserved--Reserved
0doneW0x0Write 1 to force !!INTR_STATE.done to 1.

ALERT_TEST

Table 5. otbn.ALERT_TEST fields
BitsFieldAccessResetDescription
31:2Reserved--Reserved
1recovW0x0Write 1 to trigger one alert event of this kind.
0fatalW0x0Write 1 to trigger one alert event of this kind.

CMD

Table 6. otbn.CMD fields
BitsFieldAccessResetDescription
31:8Reserved--Reserved
7:0cmdW0x0The operation to perform.

| Value | Name | Description |
|:------|:--------------|:------------|
| 0xd8 | EXECUTE | Starts the execution of the program stored in the instruction memory, starting at address zero. |
| 0xc3 | SEC_WIPE_DMEM | Securely removes all contents from the data memory. |
| 0x1e | SEC_WIPE_IMEM | Securely removes all contents from the instruction memory. |

CTRL

Table 7. otbn.CTRL fields
BitsFieldAccessResetDescription
31:1Reserved--Reserved
0software_errs_fatalRW0x0Controls the reaction to software errors.

When set software errors produce fatal errors, rather than
recoverable errors.

Writes are ignored if OTBN is not idle.

STATUS

Table 8. otbn.STATUS fields
BitsFieldAccessResetDescription
31:8Reserved--Reserved
7:0statusR0x4Indicates the current operational state OTBN is in.

All BUSY values represent an operation started by a write to the
!!CMD register.

| Value | Name | Description |
|:------|:-------------------|:------------------------------------------------------|
| 0x00 | IDLE | OTBN is idle: it is not performing any action. |
| 0x01 | BUSY_EXECUTE | OTBN is busy executing software. |
| 0x02 | BUSY_SEC_WIPE_DMEM | OTBN is busy securely wiping the data memory. |
| 0x03 | BUSY_SEC_WIPE_IMEM | OTBN is busy securely wiping the instruction memory. |
| 0x04 | BUSY_SEC_WIPE_INT | OTBN is busy securely wiping the internal state. |
| 0xFF | LOCKED | OTBN is locked as reaction to a fatal error, and must be reset to unlock it again. See also the section "Reaction to Fatal Errors". |

ERR_BITS

Table 9. otbn.ERR_BITS fields
BitsFieldAccessResetDescription
31:24Reserved--Reserved
23fatal_softwareRW0x0A `FATAL_SOFTWARE` error was observed.
22lifecycle_escalationRW0x0A `LIFECYCLE_ESCALATION` error was observed.
21illegal_bus_accessRW0x0An `ILLEGAL_BUS_ACCESS` error was observed.
20bad_internal_stateRW0x0A `BAD_INTERNAL_STATE` error was observed.
19bus_intg_violationRW0x0A `BUS_INTG_VIOLATION` error was observed.
18reg_intg_violationRW0x0A `REG_INTG_VIOLATION` error was observed.
17dmem_intg_violationRW0x0A `DMEM_INTG_VIOLATION` error was observed.
16imem_intg_violationRW0x0A `IMEM_INTG_VIOLATION` error was observed.
15:9Reserved--Reserved
8mai_software_errorRW0x0An `MAI_SOFTWARE_ERROR` error was observed.
7rnd_fips_chk_failRW0x0An `RND_FIPS_CHK_FAIL` error was observed.
6rnd_rep_chk_failRW0x0An `RND_REP_CHK_FAIL` error was observed.
5key_invalidRW0x0A `KEY_INVALID` error was observed.
4loopRW0x0A `LOOP` error was observed.
3illegal_insnRW0x0An `ILLEGAL_INSN` error was observed.
2call_stackRW0x0A `CALL_STACK` error was observed.
1bad_insn_addrRW0x0A `BAD_INSN_ADDR` error was observed.
0bad_data_addrRW0x0A `BAD_DATA_ADDR` error was observed.

FATAL_ALERT_CAUSE

Table 10. otbn.FATAL_ALERT_CAUSE fields
BitsFieldAccessResetDescription
31:8Reserved--Reserved
7fatal_softwareR0x0A `FATAL_SOFTWARE` error was observed.
6lifecycle_escalationR0x0A `LIFECYCLE_ESCALATION` error was observed.
5illegal_bus_accessR0x0A `ILLEGAL_BUS_ACCESS` error was observed.
4bad_internal_stateR0x0A `BAD_INTERNAL_STATE` error was observed.
3bus_intg_violationR0x0A `BUS_INTG_VIOLATION` error was observed.
2reg_intg_violationR0x0A `REG_INTG_VIOLATION` error was observed.
1dmem_intg_violationR0x0A `DMEM_INTG_VIOLATION` error was observed.
0imem_intg_violationR0x0A `IMEM_INTG_VIOLATION` error was observed.

INSN_CNT

Table 11. otbn.INSN_CNT fields
BitsFieldAccessResetDescription
31:0insn_cntRW0x0The number of executed instructions.

LOAD_CHECKSUM

Table 12. otbn.LOAD_CHECKSUM fields
BitsFieldAccessResetDescription
31:0checksumRW0x0Checksum accumulator