Mailbox Unit
1. Overview
The Mailbox Unit connects two software endpoints through a pair of FIFOs.
Each endpoint has a register aperture: writing WRITE_DATA sends one word to
the peer, and reading READ_DATA consumes one word sent by the peer. A single
AXI4-Lite slave port serves all pairs.
NUM_MAILBOXES counts bidirectional pairs, each with two directional apertures
and two interrupt outputs. The SMC instance provides 32 pairs (64 apertures);
the SEP instance provides 8 pairs (16 apertures). Aperture names describe intended use; both ends remain reachable
through the same slave port. Access isolation is the subsystem’s responsibility,
not a property conferred by naming an aperture inbound or outbound.
Figure 1. SMC mailbox wrapper and interrupt routing
Figure 1 shows the SMC instance of the mailbox,
u_smc_axil_mailbox, and its interrupt connections. The SMC configures 32
mailboxes of depth 2, with 32-bit address and 64-bit data. The port comes
from the mailbox target of smc_internal_axi_lite_xbar, and the unit runs on
a copy of the SMC clock that u_mailbox_cg gates while the port is idle.
The demux u_mailbox_demux, a PULP axi_lite_demux, selects one of 64
ports from address bits [16:11] above 0xC001_8000. Each mailbox,
gen_mailbox[m].u_axi_lite_mailbox, is a PULP axi_lite_mailbox; the
figure puts the source project in parentheses. Mailbox m places its outbound port at
0xC001_8000 + m × 0x1000 and its inbound port 0x800 above it.
Within a mailbox, the arrows between the ports show the direction of data:
WRITE_DATA in one port pushes the FIFO that READ_DATA in the other port
pops. The 32 inbound-port interrupts are SMC CPU interrupts 288 to 319. The
32 outbound-port interrupts leave the SMC on smc_ext_mailbox_interrupts_o,
which the SMU passes out of its boundary.
The SEP holds a second instance of this unit with eight mailboxes, described in the SEP fabric chapter. The outbound interrupts of that instance reach the SMC as peripheral interrupts 0 to 7, SMC CPU interrupts 256 to 263.
2. Architecture
The parameters and ports of axi_lite_mailbox_unit are listed in axi_lite_mailbox_unit.
2.1. Paired FIFOs
An axi_lite_demux selects one of 2 * NUM_MAILBOXES register apertures.
Within pair N, the outbound aperture writes FIFO A and reads FIFO B; the
inbound aperture writes FIFO B and reads FIFO A. The FIFOs are internal to
the unit. Flushing an aperture’s write FIFO therefore discards data its peer
would read; flushing its read FIFO discards data the peer has already sent.
WRITE_DATA enqueues one word when space is available. Inactive AXI byte lanes
are written as zero; a partial write does not merge with an existing FIFO word.
READ_DATA returns and pops the oldest received word. Software must use status
to avoid full writes and empty reads; the interface reports errors rather than
waiting for FIFO space or data. The error responses are described below.
2.2. Interrupts
Each aperture has its own WIRQT, RIRQT, IRQS, IRQEN and IRQP.
inbound_interrupt_o[N] and outbound_interrupt_o[N] are active-high level
outputs. Each is the OR of IRQP = IRQS & IRQEN for its aperture.
| IRQS bit | Source | Set condition |
|---|---|---|
0 |
Write threshold |
Occupancy of the aperture’s write FIFO is strictly greater
than |
1 |
Read threshold |
Occupancy of its read FIFO is strictly greater than |
2 |
Access error |
A full-FIFO write or empty-FIFO read. |
These status bits latch independently of IRQEN. Acknowledge selected bits by
writing ones to IRQS; reading it does not clear them. Threshold status can
reassert if the occupancy condition remains true. WIRQT and RIRQT writes
are clamped to MAILBOX_DEPTH - 1, so a threshold of zero detects any queued
word and the maximum threshold detects a full FIFO.
STATUS exposes live FIFO-empty/full and threshold conditions. It is distinct
from the latched IRQS. Reading ERROR_FLAGS clears the detailed error flags,
but does not acknowledge the shared IRQS error bit.
2.3. Clock and Reset
The unit and its FIFOs use clk_i; there is no internal clock-domain crossing.
rst_ni is asynchronous and active low. Reset empties the FIFOs and clears
thresholds, error flags, interrupt status and enables. test_en_i supplies the
AXI demultiplexer’s test input. Follow subsystem reset and access-isolation
requirements when either endpoint is active.
3. Interface and Programming
3.1. External Interface
A single AXI4-Lite slave (mailbox_axi_req_i / mailbox_axi_resp_o) serves all
apertures; its address/data widths and channel/aggregate struct types are
elaboration parameters. The inbound_interrupt_o and outbound_interrupt_o
vectors each carry NUM_MAILBOXES active-high level interrupts, one per aperture.
The full parameter and port list of axi_lite_mailbox_unit is in axi_lite_mailbox_unit.
The per-aperture B and R responses pass through spill registers. Request arbitration, arrival of both write channels, and response backpressure also affect observed latency; software must not assume a fixed completion cycle. Reads and writes use separate AXI4-Lite channels but operate on the same FIFO and status state.
3.2. Access Results
| Access | Result |
|---|---|
Read |
|
Write |
|
Read write-only |
|
Write |
Ignored with |
Access to an unmapped offset inside an aperture ( |
|
Read |
Returns and clears both detailed error flags. A new error in the same cycle is retained. |
Write |
Pulses the selected FIFO flush; the bits are not stored configuration and read back as zero. |
3.3. Sending and Receiving
The register interface does not allocate FIFO ownership to clients, and status and data accesses are not one atomic operation. The Programmer’s Guide gives the mailbox usage rules.
4. Memory Map and Register Reference
4.1. Memory Map
With the default MAILBOX_SIZE=0x800, each directional aperture occupies
2 KiB and each pair occupies 4 KiB. The SMC 32-pair map spans 0x20000
bytes, and the SEP 8-pair map spans 0x8000 bytes; the generic unit’s span is 2 * MAILBOX_SIZE * NUM_MAILBOXES.
The SMC and SEP wrapper layouts are generated from
their SystemRDL compositions:
| Address Range | Size | Decoded Extent | Unit | Instances | Stride |
|---|---|---|---|---|---|
BASE + 0x0 – BASE + 0x7FF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x800 – BASE + 0xFFF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x1000 – BASE + 0x17FF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x1800 – BASE + 0x1FFF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x2000 – BASE + 0x27FF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x2800 – BASE + 0x2FFF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x3000 – BASE + 0x37FF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x3800 – BASE + 0x3FFF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x4000 – BASE + 0x47FF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x4800 – BASE + 0x4FFF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x5000 – BASE + 0x57FF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x5800 – BASE + 0x5FFF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x6000 – BASE + 0x67FF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x6800 – BASE + 0x6FFF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x7000 – BASE + 0x77FF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x7800 – BASE + 0x7FFF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x8000 – BASE + 0x87FF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x8800 – BASE + 0x8FFF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x9000 – BASE + 0x97FF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x9800 – BASE + 0x9FFF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0xA000 – BASE + 0xA7FF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0xA800 – BASE + 0xAFFF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0xB000 – BASE + 0xB7FF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0xB800 – BASE + 0xBFFF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0xC000 – BASE + 0xC7FF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0xC800 – BASE + 0xCFFF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0xD000 – BASE + 0xD7FF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0xD800 – BASE + 0xDFFF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0xE000 – BASE + 0xE7FF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0xE800 – BASE + 0xEFFF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0xF000 – BASE + 0xF7FF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0xF800 – BASE + 0xFFFF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x10000 – BASE + 0x107FF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x10800 – BASE + 0x10FFF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x11000 – BASE + 0x117FF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x11800 – BASE + 0x11FFF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x12000 – BASE + 0x127FF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x12800 – BASE + 0x12FFF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x13000 – BASE + 0x137FF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x13800 – BASE + 0x13FFF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x14000 – BASE + 0x147FF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x14800 – BASE + 0x14FFF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x15000 – BASE + 0x157FF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x15800 – BASE + 0x15FFF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x16000 – BASE + 0x167FF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x16800 – BASE + 0x16FFF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x17000 – BASE + 0x177FF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x17800 – BASE + 0x17FFF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x18000 – BASE + 0x187FF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x18800 – BASE + 0x18FFF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x19000 – BASE + 0x197FF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x19800 – BASE + 0x19FFF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x1A000 – BASE + 0x1A7FF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x1A800 – BASE + 0x1AFFF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x1B000 – BASE + 0x1B7FF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x1B800 – BASE + 0x1BFFF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x1C000 – BASE + 0x1C7FF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x1C800 – BASE + 0x1CFFF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x1D000 – BASE + 0x1D7FF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x1D800 – BASE + 0x1DFFF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x1E000 – BASE + 0x1E7FF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x1E800 – BASE + 0x1EFFF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x1F000 – BASE + 0x1F7FF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x1F800 – BASE + 0x1FFFF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
| Address Range | Size | Decoded Extent | Unit | Instances | Stride |
|---|---|---|---|---|---|
BASE + 0x0 – BASE + 0x7FF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x800 – BASE + 0xFFF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x1000 – BASE + 0x17FF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x1800 – BASE + 0x1FFF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x2000 – BASE + 0x27FF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x2800 – BASE + 0x2FFF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x3000 – BASE + 0x37FF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x3800 – BASE + 0x3FFF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x4000 – BASE + 0x47FF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x4800 – BASE + 0x4FFF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x5000 – BASE + 0x57FF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x5800 – BASE + 0x5FFF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x6000 – BASE + 0x67FF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x6800 – BASE + 0x6FFF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x7000 – BASE + 0x77FF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
BASE + 0x7800 – BASE + 0x7FFF |
2 KiB |
80 B |
AXI-Lite Mailbox Address Map |
1 instance |
- |
4.1.1. Per-Mailbox Register Map
Each aperture contains ten registers.
Offsets are spaced by DATA_WIDTH/8, so they are 8 bytes apart in the
64-bit configurations used today. The generated detailed register map below is
authoritative for offsets, widths, access, and field descriptions. The CTRL
flush bits are pulses rather than stored state, so reads return zero with an
OKAY response.
4.1.2. Address Examples
For mailbox pair N, the outbound aperture begins at
BASE + N * 0x1000; the inbound aperture begins 0x800 bytes later. A
register address is the aperture base plus the generated register offset. For
example, in pair zero, READ_DATA is at BASE + 0x8 outbound and
BASE + 0x808 inbound.
4.2. Detailed Register Map
AXI-Lite Mailbox Address Map
Register interface for a single AXI-Lite mailbox: data FIFOs, level and status flags, and interrupt controls.
Register List:
| Address | Name | Access | Description |
|---|---|---|---|
| 0x0 | WRITE_DATA | W | - |
| 0x8 | READ_DATA | R | - |
| 0x10 | STATUS | R | - |
| 0x18 | ERROR_FLAGS | R | - |
| 0x20 | WIRQT | RW | - |
| 0x28 | RIRQT | RW | - |
| 0x30 | IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x38 | IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x40 | IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x48 | CTRL | W | - |
Register Details:
WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
4.2.1. Subsystem Wrapper Maps
The wrapper maps describe the generated SMC and SEP mailbox compositions. Their offsets are relative to the corresponding wrapper aperture.
SMC AXI-Lite Mailbox Wrapper Address Map
SMC-side wrapper instantiating the AXI-Lite mailbox pairs.
Each outbound_mailbox_N / inbound_mailbox_N pair is the two apertures of one
bidirectional mailbox and shares a single pair of FIFOs: data written through
WRITE_DATA in one aperture is what READ_DATA in the other aperture returns.
The outbound/inbound naming reflects intended use, not an access restriction.
Register List:
| Address | Name | Access | Description |
|---|---|---|---|
| 0x0 | outbound_mailbox_0.WRITE_DATA | W | - |
| 0x8 | outbound_mailbox_0.READ_DATA | R | - |
| 0x10 | outbound_mailbox_0.STATUS | R | - |
| 0x18 | outbound_mailbox_0.ERROR_FLAGS | R | - |
| 0x20 | outbound_mailbox_0.WIRQT | RW | - |
| 0x28 | outbound_mailbox_0.RIRQT | RW | - |
| 0x30 | outbound_mailbox_0.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x38 | outbound_mailbox_0.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x40 | outbound_mailbox_0.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x48 | outbound_mailbox_0.CTRL | W | - |
| 0x800 | inbound_mailbox_0.WRITE_DATA | W | - |
| 0x808 | inbound_mailbox_0.READ_DATA | R | - |
| 0x810 | inbound_mailbox_0.STATUS | R | - |
| 0x818 | inbound_mailbox_0.ERROR_FLAGS | R | - |
| 0x820 | inbound_mailbox_0.WIRQT | RW | - |
| 0x828 | inbound_mailbox_0.RIRQT | RW | - |
| 0x830 | inbound_mailbox_0.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x838 | inbound_mailbox_0.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x840 | inbound_mailbox_0.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x848 | inbound_mailbox_0.CTRL | W | - |
| 0x1000 | outbound_mailbox_1.WRITE_DATA | W | - |
| 0x1008 | outbound_mailbox_1.READ_DATA | R | - |
| 0x1010 | outbound_mailbox_1.STATUS | R | - |
| 0x1018 | outbound_mailbox_1.ERROR_FLAGS | R | - |
| 0x1020 | outbound_mailbox_1.WIRQT | RW | - |
| 0x1028 | outbound_mailbox_1.RIRQT | RW | - |
| 0x1030 | outbound_mailbox_1.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x1038 | outbound_mailbox_1.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x1040 | outbound_mailbox_1.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x1048 | outbound_mailbox_1.CTRL | W | - |
| 0x1800 | inbound_mailbox_1.WRITE_DATA | W | - |
| 0x1808 | inbound_mailbox_1.READ_DATA | R | - |
| 0x1810 | inbound_mailbox_1.STATUS | R | - |
| 0x1818 | inbound_mailbox_1.ERROR_FLAGS | R | - |
| 0x1820 | inbound_mailbox_1.WIRQT | RW | - |
| 0x1828 | inbound_mailbox_1.RIRQT | RW | - |
| 0x1830 | inbound_mailbox_1.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x1838 | inbound_mailbox_1.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x1840 | inbound_mailbox_1.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x1848 | inbound_mailbox_1.CTRL | W | - |
| 0x2000 | outbound_mailbox_2.WRITE_DATA | W | - |
| 0x2008 | outbound_mailbox_2.READ_DATA | R | - |
| 0x2010 | outbound_mailbox_2.STATUS | R | - |
| 0x2018 | outbound_mailbox_2.ERROR_FLAGS | R | - |
| 0x2020 | outbound_mailbox_2.WIRQT | RW | - |
| 0x2028 | outbound_mailbox_2.RIRQT | RW | - |
| 0x2030 | outbound_mailbox_2.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x2038 | outbound_mailbox_2.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x2040 | outbound_mailbox_2.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x2048 | outbound_mailbox_2.CTRL | W | - |
| 0x2800 | inbound_mailbox_2.WRITE_DATA | W | - |
| 0x2808 | inbound_mailbox_2.READ_DATA | R | - |
| 0x2810 | inbound_mailbox_2.STATUS | R | - |
| 0x2818 | inbound_mailbox_2.ERROR_FLAGS | R | - |
| 0x2820 | inbound_mailbox_2.WIRQT | RW | - |
| 0x2828 | inbound_mailbox_2.RIRQT | RW | - |
| 0x2830 | inbound_mailbox_2.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x2838 | inbound_mailbox_2.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x2840 | inbound_mailbox_2.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x2848 | inbound_mailbox_2.CTRL | W | - |
| 0x3000 | outbound_mailbox_3.WRITE_DATA | W | - |
| 0x3008 | outbound_mailbox_3.READ_DATA | R | - |
| 0x3010 | outbound_mailbox_3.STATUS | R | - |
| 0x3018 | outbound_mailbox_3.ERROR_FLAGS | R | - |
| 0x3020 | outbound_mailbox_3.WIRQT | RW | - |
| 0x3028 | outbound_mailbox_3.RIRQT | RW | - |
| 0x3030 | outbound_mailbox_3.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x3038 | outbound_mailbox_3.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x3040 | outbound_mailbox_3.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x3048 | outbound_mailbox_3.CTRL | W | - |
| 0x3800 | inbound_mailbox_3.WRITE_DATA | W | - |
| 0x3808 | inbound_mailbox_3.READ_DATA | R | - |
| 0x3810 | inbound_mailbox_3.STATUS | R | - |
| 0x3818 | inbound_mailbox_3.ERROR_FLAGS | R | - |
| 0x3820 | inbound_mailbox_3.WIRQT | RW | - |
| 0x3828 | inbound_mailbox_3.RIRQT | RW | - |
| 0x3830 | inbound_mailbox_3.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x3838 | inbound_mailbox_3.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x3840 | inbound_mailbox_3.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x3848 | inbound_mailbox_3.CTRL | W | - |
| 0x4000 | outbound_mailbox_4.WRITE_DATA | W | - |
| 0x4008 | outbound_mailbox_4.READ_DATA | R | - |
| 0x4010 | outbound_mailbox_4.STATUS | R | - |
| 0x4018 | outbound_mailbox_4.ERROR_FLAGS | R | - |
| 0x4020 | outbound_mailbox_4.WIRQT | RW | - |
| 0x4028 | outbound_mailbox_4.RIRQT | RW | - |
| 0x4030 | outbound_mailbox_4.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x4038 | outbound_mailbox_4.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x4040 | outbound_mailbox_4.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x4048 | outbound_mailbox_4.CTRL | W | - |
| 0x4800 | inbound_mailbox_4.WRITE_DATA | W | - |
| 0x4808 | inbound_mailbox_4.READ_DATA | R | - |
| 0x4810 | inbound_mailbox_4.STATUS | R | - |
| 0x4818 | inbound_mailbox_4.ERROR_FLAGS | R | - |
| 0x4820 | inbound_mailbox_4.WIRQT | RW | - |
| 0x4828 | inbound_mailbox_4.RIRQT | RW | - |
| 0x4830 | inbound_mailbox_4.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x4838 | inbound_mailbox_4.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x4840 | inbound_mailbox_4.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x4848 | inbound_mailbox_4.CTRL | W | - |
| 0x5000 | outbound_mailbox_5.WRITE_DATA | W | - |
| 0x5008 | outbound_mailbox_5.READ_DATA | R | - |
| 0x5010 | outbound_mailbox_5.STATUS | R | - |
| 0x5018 | outbound_mailbox_5.ERROR_FLAGS | R | - |
| 0x5020 | outbound_mailbox_5.WIRQT | RW | - |
| 0x5028 | outbound_mailbox_5.RIRQT | RW | - |
| 0x5030 | outbound_mailbox_5.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x5038 | outbound_mailbox_5.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x5040 | outbound_mailbox_5.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x5048 | outbound_mailbox_5.CTRL | W | - |
| 0x5800 | inbound_mailbox_5.WRITE_DATA | W | - |
| 0x5808 | inbound_mailbox_5.READ_DATA | R | - |
| 0x5810 | inbound_mailbox_5.STATUS | R | - |
| 0x5818 | inbound_mailbox_5.ERROR_FLAGS | R | - |
| 0x5820 | inbound_mailbox_5.WIRQT | RW | - |
| 0x5828 | inbound_mailbox_5.RIRQT | RW | - |
| 0x5830 | inbound_mailbox_5.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x5838 | inbound_mailbox_5.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x5840 | inbound_mailbox_5.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x5848 | inbound_mailbox_5.CTRL | W | - |
| 0x6000 | outbound_mailbox_6.WRITE_DATA | W | - |
| 0x6008 | outbound_mailbox_6.READ_DATA | R | - |
| 0x6010 | outbound_mailbox_6.STATUS | R | - |
| 0x6018 | outbound_mailbox_6.ERROR_FLAGS | R | - |
| 0x6020 | outbound_mailbox_6.WIRQT | RW | - |
| 0x6028 | outbound_mailbox_6.RIRQT | RW | - |
| 0x6030 | outbound_mailbox_6.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x6038 | outbound_mailbox_6.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x6040 | outbound_mailbox_6.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x6048 | outbound_mailbox_6.CTRL | W | - |
| 0x6800 | inbound_mailbox_6.WRITE_DATA | W | - |
| 0x6808 | inbound_mailbox_6.READ_DATA | R | - |
| 0x6810 | inbound_mailbox_6.STATUS | R | - |
| 0x6818 | inbound_mailbox_6.ERROR_FLAGS | R | - |
| 0x6820 | inbound_mailbox_6.WIRQT | RW | - |
| 0x6828 | inbound_mailbox_6.RIRQT | RW | - |
| 0x6830 | inbound_mailbox_6.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x6838 | inbound_mailbox_6.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x6840 | inbound_mailbox_6.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x6848 | inbound_mailbox_6.CTRL | W | - |
| 0x7000 | outbound_mailbox_7.WRITE_DATA | W | - |
| 0x7008 | outbound_mailbox_7.READ_DATA | R | - |
| 0x7010 | outbound_mailbox_7.STATUS | R | - |
| 0x7018 | outbound_mailbox_7.ERROR_FLAGS | R | - |
| 0x7020 | outbound_mailbox_7.WIRQT | RW | - |
| 0x7028 | outbound_mailbox_7.RIRQT | RW | - |
| 0x7030 | outbound_mailbox_7.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x7038 | outbound_mailbox_7.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x7040 | outbound_mailbox_7.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x7048 | outbound_mailbox_7.CTRL | W | - |
| 0x7800 | inbound_mailbox_7.WRITE_DATA | W | - |
| 0x7808 | inbound_mailbox_7.READ_DATA | R | - |
| 0x7810 | inbound_mailbox_7.STATUS | R | - |
| 0x7818 | inbound_mailbox_7.ERROR_FLAGS | R | - |
| 0x7820 | inbound_mailbox_7.WIRQT | RW | - |
| 0x7828 | inbound_mailbox_7.RIRQT | RW | - |
| 0x7830 | inbound_mailbox_7.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x7838 | inbound_mailbox_7.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x7840 | inbound_mailbox_7.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x7848 | inbound_mailbox_7.CTRL | W | - |
| 0x8000 | outbound_mailbox_8.WRITE_DATA | W | - |
| 0x8008 | outbound_mailbox_8.READ_DATA | R | - |
| 0x8010 | outbound_mailbox_8.STATUS | R | - |
| 0x8018 | outbound_mailbox_8.ERROR_FLAGS | R | - |
| 0x8020 | outbound_mailbox_8.WIRQT | RW | - |
| 0x8028 | outbound_mailbox_8.RIRQT | RW | - |
| 0x8030 | outbound_mailbox_8.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x8038 | outbound_mailbox_8.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x8040 | outbound_mailbox_8.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x8048 | outbound_mailbox_8.CTRL | W | - |
| 0x8800 | inbound_mailbox_8.WRITE_DATA | W | - |
| 0x8808 | inbound_mailbox_8.READ_DATA | R | - |
| 0x8810 | inbound_mailbox_8.STATUS | R | - |
| 0x8818 | inbound_mailbox_8.ERROR_FLAGS | R | - |
| 0x8820 | inbound_mailbox_8.WIRQT | RW | - |
| 0x8828 | inbound_mailbox_8.RIRQT | RW | - |
| 0x8830 | inbound_mailbox_8.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x8838 | inbound_mailbox_8.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x8840 | inbound_mailbox_8.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x8848 | inbound_mailbox_8.CTRL | W | - |
| 0x9000 | outbound_mailbox_9.WRITE_DATA | W | - |
| 0x9008 | outbound_mailbox_9.READ_DATA | R | - |
| 0x9010 | outbound_mailbox_9.STATUS | R | - |
| 0x9018 | outbound_mailbox_9.ERROR_FLAGS | R | - |
| 0x9020 | outbound_mailbox_9.WIRQT | RW | - |
| 0x9028 | outbound_mailbox_9.RIRQT | RW | - |
| 0x9030 | outbound_mailbox_9.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x9038 | outbound_mailbox_9.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x9040 | outbound_mailbox_9.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x9048 | outbound_mailbox_9.CTRL | W | - |
| 0x9800 | inbound_mailbox_9.WRITE_DATA | W | - |
| 0x9808 | inbound_mailbox_9.READ_DATA | R | - |
| 0x9810 | inbound_mailbox_9.STATUS | R | - |
| 0x9818 | inbound_mailbox_9.ERROR_FLAGS | R | - |
| 0x9820 | inbound_mailbox_9.WIRQT | RW | - |
| 0x9828 | inbound_mailbox_9.RIRQT | RW | - |
| 0x9830 | inbound_mailbox_9.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x9838 | inbound_mailbox_9.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x9840 | inbound_mailbox_9.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x9848 | inbound_mailbox_9.CTRL | W | - |
| 0xA000 | outbound_mailbox_10.WRITE_DATA | W | - |
| 0xA008 | outbound_mailbox_10.READ_DATA | R | - |
| 0xA010 | outbound_mailbox_10.STATUS | R | - |
| 0xA018 | outbound_mailbox_10.ERROR_FLAGS | R | - |
| 0xA020 | outbound_mailbox_10.WIRQT | RW | - |
| 0xA028 | outbound_mailbox_10.RIRQT | RW | - |
| 0xA030 | outbound_mailbox_10.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0xA038 | outbound_mailbox_10.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0xA040 | outbound_mailbox_10.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0xA048 | outbound_mailbox_10.CTRL | W | - |
| 0xA800 | inbound_mailbox_10.WRITE_DATA | W | - |
| 0xA808 | inbound_mailbox_10.READ_DATA | R | - |
| 0xA810 | inbound_mailbox_10.STATUS | R | - |
| 0xA818 | inbound_mailbox_10.ERROR_FLAGS | R | - |
| 0xA820 | inbound_mailbox_10.WIRQT | RW | - |
| 0xA828 | inbound_mailbox_10.RIRQT | RW | - |
| 0xA830 | inbound_mailbox_10.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0xA838 | inbound_mailbox_10.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0xA840 | inbound_mailbox_10.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0xA848 | inbound_mailbox_10.CTRL | W | - |
| 0xB000 | outbound_mailbox_11.WRITE_DATA | W | - |
| 0xB008 | outbound_mailbox_11.READ_DATA | R | - |
| 0xB010 | outbound_mailbox_11.STATUS | R | - |
| 0xB018 | outbound_mailbox_11.ERROR_FLAGS | R | - |
| 0xB020 | outbound_mailbox_11.WIRQT | RW | - |
| 0xB028 | outbound_mailbox_11.RIRQT | RW | - |
| 0xB030 | outbound_mailbox_11.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0xB038 | outbound_mailbox_11.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0xB040 | outbound_mailbox_11.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0xB048 | outbound_mailbox_11.CTRL | W | - |
| 0xB800 | inbound_mailbox_11.WRITE_DATA | W | - |
| 0xB808 | inbound_mailbox_11.READ_DATA | R | - |
| 0xB810 | inbound_mailbox_11.STATUS | R | - |
| 0xB818 | inbound_mailbox_11.ERROR_FLAGS | R | - |
| 0xB820 | inbound_mailbox_11.WIRQT | RW | - |
| 0xB828 | inbound_mailbox_11.RIRQT | RW | - |
| 0xB830 | inbound_mailbox_11.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0xB838 | inbound_mailbox_11.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0xB840 | inbound_mailbox_11.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0xB848 | inbound_mailbox_11.CTRL | W | - |
| 0xC000 | outbound_mailbox_12.WRITE_DATA | W | - |
| 0xC008 | outbound_mailbox_12.READ_DATA | R | - |
| 0xC010 | outbound_mailbox_12.STATUS | R | - |
| 0xC018 | outbound_mailbox_12.ERROR_FLAGS | R | - |
| 0xC020 | outbound_mailbox_12.WIRQT | RW | - |
| 0xC028 | outbound_mailbox_12.RIRQT | RW | - |
| 0xC030 | outbound_mailbox_12.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0xC038 | outbound_mailbox_12.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0xC040 | outbound_mailbox_12.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0xC048 | outbound_mailbox_12.CTRL | W | - |
| 0xC800 | inbound_mailbox_12.WRITE_DATA | W | - |
| 0xC808 | inbound_mailbox_12.READ_DATA | R | - |
| 0xC810 | inbound_mailbox_12.STATUS | R | - |
| 0xC818 | inbound_mailbox_12.ERROR_FLAGS | R | - |
| 0xC820 | inbound_mailbox_12.WIRQT | RW | - |
| 0xC828 | inbound_mailbox_12.RIRQT | RW | - |
| 0xC830 | inbound_mailbox_12.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0xC838 | inbound_mailbox_12.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0xC840 | inbound_mailbox_12.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0xC848 | inbound_mailbox_12.CTRL | W | - |
| 0xD000 | outbound_mailbox_13.WRITE_DATA | W | - |
| 0xD008 | outbound_mailbox_13.READ_DATA | R | - |
| 0xD010 | outbound_mailbox_13.STATUS | R | - |
| 0xD018 | outbound_mailbox_13.ERROR_FLAGS | R | - |
| 0xD020 | outbound_mailbox_13.WIRQT | RW | - |
| 0xD028 | outbound_mailbox_13.RIRQT | RW | - |
| 0xD030 | outbound_mailbox_13.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0xD038 | outbound_mailbox_13.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0xD040 | outbound_mailbox_13.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0xD048 | outbound_mailbox_13.CTRL | W | - |
| 0xD800 | inbound_mailbox_13.WRITE_DATA | W | - |
| 0xD808 | inbound_mailbox_13.READ_DATA | R | - |
| 0xD810 | inbound_mailbox_13.STATUS | R | - |
| 0xD818 | inbound_mailbox_13.ERROR_FLAGS | R | - |
| 0xD820 | inbound_mailbox_13.WIRQT | RW | - |
| 0xD828 | inbound_mailbox_13.RIRQT | RW | - |
| 0xD830 | inbound_mailbox_13.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0xD838 | inbound_mailbox_13.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0xD840 | inbound_mailbox_13.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0xD848 | inbound_mailbox_13.CTRL | W | - |
| 0xE000 | outbound_mailbox_14.WRITE_DATA | W | - |
| 0xE008 | outbound_mailbox_14.READ_DATA | R | - |
| 0xE010 | outbound_mailbox_14.STATUS | R | - |
| 0xE018 | outbound_mailbox_14.ERROR_FLAGS | R | - |
| 0xE020 | outbound_mailbox_14.WIRQT | RW | - |
| 0xE028 | outbound_mailbox_14.RIRQT | RW | - |
| 0xE030 | outbound_mailbox_14.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0xE038 | outbound_mailbox_14.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0xE040 | outbound_mailbox_14.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0xE048 | outbound_mailbox_14.CTRL | W | - |
| 0xE800 | inbound_mailbox_14.WRITE_DATA | W | - |
| 0xE808 | inbound_mailbox_14.READ_DATA | R | - |
| 0xE810 | inbound_mailbox_14.STATUS | R | - |
| 0xE818 | inbound_mailbox_14.ERROR_FLAGS | R | - |
| 0xE820 | inbound_mailbox_14.WIRQT | RW | - |
| 0xE828 | inbound_mailbox_14.RIRQT | RW | - |
| 0xE830 | inbound_mailbox_14.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0xE838 | inbound_mailbox_14.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0xE840 | inbound_mailbox_14.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0xE848 | inbound_mailbox_14.CTRL | W | - |
| 0xF000 | outbound_mailbox_15.WRITE_DATA | W | - |
| 0xF008 | outbound_mailbox_15.READ_DATA | R | - |
| 0xF010 | outbound_mailbox_15.STATUS | R | - |
| 0xF018 | outbound_mailbox_15.ERROR_FLAGS | R | - |
| 0xF020 | outbound_mailbox_15.WIRQT | RW | - |
| 0xF028 | outbound_mailbox_15.RIRQT | RW | - |
| 0xF030 | outbound_mailbox_15.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0xF038 | outbound_mailbox_15.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0xF040 | outbound_mailbox_15.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0xF048 | outbound_mailbox_15.CTRL | W | - |
| 0xF800 | inbound_mailbox_15.WRITE_DATA | W | - |
| 0xF808 | inbound_mailbox_15.READ_DATA | R | - |
| 0xF810 | inbound_mailbox_15.STATUS | R | - |
| 0xF818 | inbound_mailbox_15.ERROR_FLAGS | R | - |
| 0xF820 | inbound_mailbox_15.WIRQT | RW | - |
| 0xF828 | inbound_mailbox_15.RIRQT | RW | - |
| 0xF830 | inbound_mailbox_15.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0xF838 | inbound_mailbox_15.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0xF840 | inbound_mailbox_15.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0xF848 | inbound_mailbox_15.CTRL | W | - |
| 0x10000 | outbound_mailbox_16.WRITE_DATA | W | - |
| 0x10008 | outbound_mailbox_16.READ_DATA | R | - |
| 0x10010 | outbound_mailbox_16.STATUS | R | - |
| 0x10018 | outbound_mailbox_16.ERROR_FLAGS | R | - |
| 0x10020 | outbound_mailbox_16.WIRQT | RW | - |
| 0x10028 | outbound_mailbox_16.RIRQT | RW | - |
| 0x10030 | outbound_mailbox_16.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x10038 | outbound_mailbox_16.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x10040 | outbound_mailbox_16.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x10048 | outbound_mailbox_16.CTRL | W | - |
| 0x10800 | inbound_mailbox_16.WRITE_DATA | W | - |
| 0x10808 | inbound_mailbox_16.READ_DATA | R | - |
| 0x10810 | inbound_mailbox_16.STATUS | R | - |
| 0x10818 | inbound_mailbox_16.ERROR_FLAGS | R | - |
| 0x10820 | inbound_mailbox_16.WIRQT | RW | - |
| 0x10828 | inbound_mailbox_16.RIRQT | RW | - |
| 0x10830 | inbound_mailbox_16.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x10838 | inbound_mailbox_16.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x10840 | inbound_mailbox_16.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x10848 | inbound_mailbox_16.CTRL | W | - |
| 0x11000 | outbound_mailbox_17.WRITE_DATA | W | - |
| 0x11008 | outbound_mailbox_17.READ_DATA | R | - |
| 0x11010 | outbound_mailbox_17.STATUS | R | - |
| 0x11018 | outbound_mailbox_17.ERROR_FLAGS | R | - |
| 0x11020 | outbound_mailbox_17.WIRQT | RW | - |
| 0x11028 | outbound_mailbox_17.RIRQT | RW | - |
| 0x11030 | outbound_mailbox_17.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x11038 | outbound_mailbox_17.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x11040 | outbound_mailbox_17.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x11048 | outbound_mailbox_17.CTRL | W | - |
| 0x11800 | inbound_mailbox_17.WRITE_DATA | W | - |
| 0x11808 | inbound_mailbox_17.READ_DATA | R | - |
| 0x11810 | inbound_mailbox_17.STATUS | R | - |
| 0x11818 | inbound_mailbox_17.ERROR_FLAGS | R | - |
| 0x11820 | inbound_mailbox_17.WIRQT | RW | - |
| 0x11828 | inbound_mailbox_17.RIRQT | RW | - |
| 0x11830 | inbound_mailbox_17.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x11838 | inbound_mailbox_17.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x11840 | inbound_mailbox_17.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x11848 | inbound_mailbox_17.CTRL | W | - |
| 0x12000 | outbound_mailbox_18.WRITE_DATA | W | - |
| 0x12008 | outbound_mailbox_18.READ_DATA | R | - |
| 0x12010 | outbound_mailbox_18.STATUS | R | - |
| 0x12018 | outbound_mailbox_18.ERROR_FLAGS | R | - |
| 0x12020 | outbound_mailbox_18.WIRQT | RW | - |
| 0x12028 | outbound_mailbox_18.RIRQT | RW | - |
| 0x12030 | outbound_mailbox_18.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x12038 | outbound_mailbox_18.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x12040 | outbound_mailbox_18.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x12048 | outbound_mailbox_18.CTRL | W | - |
| 0x12800 | inbound_mailbox_18.WRITE_DATA | W | - |
| 0x12808 | inbound_mailbox_18.READ_DATA | R | - |
| 0x12810 | inbound_mailbox_18.STATUS | R | - |
| 0x12818 | inbound_mailbox_18.ERROR_FLAGS | R | - |
| 0x12820 | inbound_mailbox_18.WIRQT | RW | - |
| 0x12828 | inbound_mailbox_18.RIRQT | RW | - |
| 0x12830 | inbound_mailbox_18.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x12838 | inbound_mailbox_18.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x12840 | inbound_mailbox_18.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x12848 | inbound_mailbox_18.CTRL | W | - |
| 0x13000 | outbound_mailbox_19.WRITE_DATA | W | - |
| 0x13008 | outbound_mailbox_19.READ_DATA | R | - |
| 0x13010 | outbound_mailbox_19.STATUS | R | - |
| 0x13018 | outbound_mailbox_19.ERROR_FLAGS | R | - |
| 0x13020 | outbound_mailbox_19.WIRQT | RW | - |
| 0x13028 | outbound_mailbox_19.RIRQT | RW | - |
| 0x13030 | outbound_mailbox_19.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x13038 | outbound_mailbox_19.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x13040 | outbound_mailbox_19.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x13048 | outbound_mailbox_19.CTRL | W | - |
| 0x13800 | inbound_mailbox_19.WRITE_DATA | W | - |
| 0x13808 | inbound_mailbox_19.READ_DATA | R | - |
| 0x13810 | inbound_mailbox_19.STATUS | R | - |
| 0x13818 | inbound_mailbox_19.ERROR_FLAGS | R | - |
| 0x13820 | inbound_mailbox_19.WIRQT | RW | - |
| 0x13828 | inbound_mailbox_19.RIRQT | RW | - |
| 0x13830 | inbound_mailbox_19.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x13838 | inbound_mailbox_19.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x13840 | inbound_mailbox_19.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x13848 | inbound_mailbox_19.CTRL | W | - |
| 0x14000 | outbound_mailbox_20.WRITE_DATA | W | - |
| 0x14008 | outbound_mailbox_20.READ_DATA | R | - |
| 0x14010 | outbound_mailbox_20.STATUS | R | - |
| 0x14018 | outbound_mailbox_20.ERROR_FLAGS | R | - |
| 0x14020 | outbound_mailbox_20.WIRQT | RW | - |
| 0x14028 | outbound_mailbox_20.RIRQT | RW | - |
| 0x14030 | outbound_mailbox_20.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x14038 | outbound_mailbox_20.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x14040 | outbound_mailbox_20.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x14048 | outbound_mailbox_20.CTRL | W | - |
| 0x14800 | inbound_mailbox_20.WRITE_DATA | W | - |
| 0x14808 | inbound_mailbox_20.READ_DATA | R | - |
| 0x14810 | inbound_mailbox_20.STATUS | R | - |
| 0x14818 | inbound_mailbox_20.ERROR_FLAGS | R | - |
| 0x14820 | inbound_mailbox_20.WIRQT | RW | - |
| 0x14828 | inbound_mailbox_20.RIRQT | RW | - |
| 0x14830 | inbound_mailbox_20.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x14838 | inbound_mailbox_20.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x14840 | inbound_mailbox_20.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x14848 | inbound_mailbox_20.CTRL | W | - |
| 0x15000 | outbound_mailbox_21.WRITE_DATA | W | - |
| 0x15008 | outbound_mailbox_21.READ_DATA | R | - |
| 0x15010 | outbound_mailbox_21.STATUS | R | - |
| 0x15018 | outbound_mailbox_21.ERROR_FLAGS | R | - |
| 0x15020 | outbound_mailbox_21.WIRQT | RW | - |
| 0x15028 | outbound_mailbox_21.RIRQT | RW | - |
| 0x15030 | outbound_mailbox_21.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x15038 | outbound_mailbox_21.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x15040 | outbound_mailbox_21.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x15048 | outbound_mailbox_21.CTRL | W | - |
| 0x15800 | inbound_mailbox_21.WRITE_DATA | W | - |
| 0x15808 | inbound_mailbox_21.READ_DATA | R | - |
| 0x15810 | inbound_mailbox_21.STATUS | R | - |
| 0x15818 | inbound_mailbox_21.ERROR_FLAGS | R | - |
| 0x15820 | inbound_mailbox_21.WIRQT | RW | - |
| 0x15828 | inbound_mailbox_21.RIRQT | RW | - |
| 0x15830 | inbound_mailbox_21.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x15838 | inbound_mailbox_21.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x15840 | inbound_mailbox_21.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x15848 | inbound_mailbox_21.CTRL | W | - |
| 0x16000 | outbound_mailbox_22.WRITE_DATA | W | - |
| 0x16008 | outbound_mailbox_22.READ_DATA | R | - |
| 0x16010 | outbound_mailbox_22.STATUS | R | - |
| 0x16018 | outbound_mailbox_22.ERROR_FLAGS | R | - |
| 0x16020 | outbound_mailbox_22.WIRQT | RW | - |
| 0x16028 | outbound_mailbox_22.RIRQT | RW | - |
| 0x16030 | outbound_mailbox_22.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x16038 | outbound_mailbox_22.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x16040 | outbound_mailbox_22.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x16048 | outbound_mailbox_22.CTRL | W | - |
| 0x16800 | inbound_mailbox_22.WRITE_DATA | W | - |
| 0x16808 | inbound_mailbox_22.READ_DATA | R | - |
| 0x16810 | inbound_mailbox_22.STATUS | R | - |
| 0x16818 | inbound_mailbox_22.ERROR_FLAGS | R | - |
| 0x16820 | inbound_mailbox_22.WIRQT | RW | - |
| 0x16828 | inbound_mailbox_22.RIRQT | RW | - |
| 0x16830 | inbound_mailbox_22.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x16838 | inbound_mailbox_22.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x16840 | inbound_mailbox_22.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x16848 | inbound_mailbox_22.CTRL | W | - |
| 0x17000 | outbound_mailbox_23.WRITE_DATA | W | - |
| 0x17008 | outbound_mailbox_23.READ_DATA | R | - |
| 0x17010 | outbound_mailbox_23.STATUS | R | - |
| 0x17018 | outbound_mailbox_23.ERROR_FLAGS | R | - |
| 0x17020 | outbound_mailbox_23.WIRQT | RW | - |
| 0x17028 | outbound_mailbox_23.RIRQT | RW | - |
| 0x17030 | outbound_mailbox_23.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x17038 | outbound_mailbox_23.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x17040 | outbound_mailbox_23.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x17048 | outbound_mailbox_23.CTRL | W | - |
| 0x17800 | inbound_mailbox_23.WRITE_DATA | W | - |
| 0x17808 | inbound_mailbox_23.READ_DATA | R | - |
| 0x17810 | inbound_mailbox_23.STATUS | R | - |
| 0x17818 | inbound_mailbox_23.ERROR_FLAGS | R | - |
| 0x17820 | inbound_mailbox_23.WIRQT | RW | - |
| 0x17828 | inbound_mailbox_23.RIRQT | RW | - |
| 0x17830 | inbound_mailbox_23.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x17838 | inbound_mailbox_23.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x17840 | inbound_mailbox_23.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x17848 | inbound_mailbox_23.CTRL | W | - |
| 0x18000 | outbound_mailbox_24.WRITE_DATA | W | - |
| 0x18008 | outbound_mailbox_24.READ_DATA | R | - |
| 0x18010 | outbound_mailbox_24.STATUS | R | - |
| 0x18018 | outbound_mailbox_24.ERROR_FLAGS | R | - |
| 0x18020 | outbound_mailbox_24.WIRQT | RW | - |
| 0x18028 | outbound_mailbox_24.RIRQT | RW | - |
| 0x18030 | outbound_mailbox_24.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x18038 | outbound_mailbox_24.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x18040 | outbound_mailbox_24.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x18048 | outbound_mailbox_24.CTRL | W | - |
| 0x18800 | inbound_mailbox_24.WRITE_DATA | W | - |
| 0x18808 | inbound_mailbox_24.READ_DATA | R | - |
| 0x18810 | inbound_mailbox_24.STATUS | R | - |
| 0x18818 | inbound_mailbox_24.ERROR_FLAGS | R | - |
| 0x18820 | inbound_mailbox_24.WIRQT | RW | - |
| 0x18828 | inbound_mailbox_24.RIRQT | RW | - |
| 0x18830 | inbound_mailbox_24.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x18838 | inbound_mailbox_24.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x18840 | inbound_mailbox_24.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x18848 | inbound_mailbox_24.CTRL | W | - |
| 0x19000 | outbound_mailbox_25.WRITE_DATA | W | - |
| 0x19008 | outbound_mailbox_25.READ_DATA | R | - |
| 0x19010 | outbound_mailbox_25.STATUS | R | - |
| 0x19018 | outbound_mailbox_25.ERROR_FLAGS | R | - |
| 0x19020 | outbound_mailbox_25.WIRQT | RW | - |
| 0x19028 | outbound_mailbox_25.RIRQT | RW | - |
| 0x19030 | outbound_mailbox_25.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x19038 | outbound_mailbox_25.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x19040 | outbound_mailbox_25.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x19048 | outbound_mailbox_25.CTRL | W | - |
| 0x19800 | inbound_mailbox_25.WRITE_DATA | W | - |
| 0x19808 | inbound_mailbox_25.READ_DATA | R | - |
| 0x19810 | inbound_mailbox_25.STATUS | R | - |
| 0x19818 | inbound_mailbox_25.ERROR_FLAGS | R | - |
| 0x19820 | inbound_mailbox_25.WIRQT | RW | - |
| 0x19828 | inbound_mailbox_25.RIRQT | RW | - |
| 0x19830 | inbound_mailbox_25.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x19838 | inbound_mailbox_25.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x19840 | inbound_mailbox_25.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x19848 | inbound_mailbox_25.CTRL | W | - |
| 0x1A000 | outbound_mailbox_26.WRITE_DATA | W | - |
| 0x1A008 | outbound_mailbox_26.READ_DATA | R | - |
| 0x1A010 | outbound_mailbox_26.STATUS | R | - |
| 0x1A018 | outbound_mailbox_26.ERROR_FLAGS | R | - |
| 0x1A020 | outbound_mailbox_26.WIRQT | RW | - |
| 0x1A028 | outbound_mailbox_26.RIRQT | RW | - |
| 0x1A030 | outbound_mailbox_26.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x1A038 | outbound_mailbox_26.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x1A040 | outbound_mailbox_26.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x1A048 | outbound_mailbox_26.CTRL | W | - |
| 0x1A800 | inbound_mailbox_26.WRITE_DATA | W | - |
| 0x1A808 | inbound_mailbox_26.READ_DATA | R | - |
| 0x1A810 | inbound_mailbox_26.STATUS | R | - |
| 0x1A818 | inbound_mailbox_26.ERROR_FLAGS | R | - |
| 0x1A820 | inbound_mailbox_26.WIRQT | RW | - |
| 0x1A828 | inbound_mailbox_26.RIRQT | RW | - |
| 0x1A830 | inbound_mailbox_26.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x1A838 | inbound_mailbox_26.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x1A840 | inbound_mailbox_26.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x1A848 | inbound_mailbox_26.CTRL | W | - |
| 0x1B000 | outbound_mailbox_27.WRITE_DATA | W | - |
| 0x1B008 | outbound_mailbox_27.READ_DATA | R | - |
| 0x1B010 | outbound_mailbox_27.STATUS | R | - |
| 0x1B018 | outbound_mailbox_27.ERROR_FLAGS | R | - |
| 0x1B020 | outbound_mailbox_27.WIRQT | RW | - |
| 0x1B028 | outbound_mailbox_27.RIRQT | RW | - |
| 0x1B030 | outbound_mailbox_27.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x1B038 | outbound_mailbox_27.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x1B040 | outbound_mailbox_27.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x1B048 | outbound_mailbox_27.CTRL | W | - |
| 0x1B800 | inbound_mailbox_27.WRITE_DATA | W | - |
| 0x1B808 | inbound_mailbox_27.READ_DATA | R | - |
| 0x1B810 | inbound_mailbox_27.STATUS | R | - |
| 0x1B818 | inbound_mailbox_27.ERROR_FLAGS | R | - |
| 0x1B820 | inbound_mailbox_27.WIRQT | RW | - |
| 0x1B828 | inbound_mailbox_27.RIRQT | RW | - |
| 0x1B830 | inbound_mailbox_27.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x1B838 | inbound_mailbox_27.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x1B840 | inbound_mailbox_27.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x1B848 | inbound_mailbox_27.CTRL | W | - |
| 0x1C000 | outbound_mailbox_28.WRITE_DATA | W | - |
| 0x1C008 | outbound_mailbox_28.READ_DATA | R | - |
| 0x1C010 | outbound_mailbox_28.STATUS | R | - |
| 0x1C018 | outbound_mailbox_28.ERROR_FLAGS | R | - |
| 0x1C020 | outbound_mailbox_28.WIRQT | RW | - |
| 0x1C028 | outbound_mailbox_28.RIRQT | RW | - |
| 0x1C030 | outbound_mailbox_28.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x1C038 | outbound_mailbox_28.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x1C040 | outbound_mailbox_28.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x1C048 | outbound_mailbox_28.CTRL | W | - |
| 0x1C800 | inbound_mailbox_28.WRITE_DATA | W | - |
| 0x1C808 | inbound_mailbox_28.READ_DATA | R | - |
| 0x1C810 | inbound_mailbox_28.STATUS | R | - |
| 0x1C818 | inbound_mailbox_28.ERROR_FLAGS | R | - |
| 0x1C820 | inbound_mailbox_28.WIRQT | RW | - |
| 0x1C828 | inbound_mailbox_28.RIRQT | RW | - |
| 0x1C830 | inbound_mailbox_28.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x1C838 | inbound_mailbox_28.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x1C840 | inbound_mailbox_28.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x1C848 | inbound_mailbox_28.CTRL | W | - |
| 0x1D000 | outbound_mailbox_29.WRITE_DATA | W | - |
| 0x1D008 | outbound_mailbox_29.READ_DATA | R | - |
| 0x1D010 | outbound_mailbox_29.STATUS | R | - |
| 0x1D018 | outbound_mailbox_29.ERROR_FLAGS | R | - |
| 0x1D020 | outbound_mailbox_29.WIRQT | RW | - |
| 0x1D028 | outbound_mailbox_29.RIRQT | RW | - |
| 0x1D030 | outbound_mailbox_29.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x1D038 | outbound_mailbox_29.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x1D040 | outbound_mailbox_29.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x1D048 | outbound_mailbox_29.CTRL | W | - |
| 0x1D800 | inbound_mailbox_29.WRITE_DATA | W | - |
| 0x1D808 | inbound_mailbox_29.READ_DATA | R | - |
| 0x1D810 | inbound_mailbox_29.STATUS | R | - |
| 0x1D818 | inbound_mailbox_29.ERROR_FLAGS | R | - |
| 0x1D820 | inbound_mailbox_29.WIRQT | RW | - |
| 0x1D828 | inbound_mailbox_29.RIRQT | RW | - |
| 0x1D830 | inbound_mailbox_29.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x1D838 | inbound_mailbox_29.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x1D840 | inbound_mailbox_29.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x1D848 | inbound_mailbox_29.CTRL | W | - |
| 0x1E000 | outbound_mailbox_30.WRITE_DATA | W | - |
| 0x1E008 | outbound_mailbox_30.READ_DATA | R | - |
| 0x1E010 | outbound_mailbox_30.STATUS | R | - |
| 0x1E018 | outbound_mailbox_30.ERROR_FLAGS | R | - |
| 0x1E020 | outbound_mailbox_30.WIRQT | RW | - |
| 0x1E028 | outbound_mailbox_30.RIRQT | RW | - |
| 0x1E030 | outbound_mailbox_30.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x1E038 | outbound_mailbox_30.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x1E040 | outbound_mailbox_30.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x1E048 | outbound_mailbox_30.CTRL | W | - |
| 0x1E800 | inbound_mailbox_30.WRITE_DATA | W | - |
| 0x1E808 | inbound_mailbox_30.READ_DATA | R | - |
| 0x1E810 | inbound_mailbox_30.STATUS | R | - |
| 0x1E818 | inbound_mailbox_30.ERROR_FLAGS | R | - |
| 0x1E820 | inbound_mailbox_30.WIRQT | RW | - |
| 0x1E828 | inbound_mailbox_30.RIRQT | RW | - |
| 0x1E830 | inbound_mailbox_30.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x1E838 | inbound_mailbox_30.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x1E840 | inbound_mailbox_30.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x1E848 | inbound_mailbox_30.CTRL | W | - |
| 0x1F000 | outbound_mailbox_31.WRITE_DATA | W | - |
| 0x1F008 | outbound_mailbox_31.READ_DATA | R | - |
| 0x1F010 | outbound_mailbox_31.STATUS | R | - |
| 0x1F018 | outbound_mailbox_31.ERROR_FLAGS | R | - |
| 0x1F020 | outbound_mailbox_31.WIRQT | RW | - |
| 0x1F028 | outbound_mailbox_31.RIRQT | RW | - |
| 0x1F030 | outbound_mailbox_31.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x1F038 | outbound_mailbox_31.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x1F040 | outbound_mailbox_31.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x1F048 | outbound_mailbox_31.CTRL | W | - |
| 0x1F800 | inbound_mailbox_31.WRITE_DATA | W | - |
| 0x1F808 | inbound_mailbox_31.READ_DATA | R | - |
| 0x1F810 | inbound_mailbox_31.STATUS | R | - |
| 0x1F818 | inbound_mailbox_31.ERROR_FLAGS | R | - |
| 0x1F820 | inbound_mailbox_31.WIRQT | RW | - |
| 0x1F828 | inbound_mailbox_31.RIRQT | RW | - |
| 0x1F830 | inbound_mailbox_31.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x1F838 | inbound_mailbox_31.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x1F840 | inbound_mailbox_31.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x1F848 | inbound_mailbox_31.CTRL | W | - |
Register Details:
outbound_mailbox_0.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
outbound_mailbox_0.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
outbound_mailbox_0.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
outbound_mailbox_0.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
outbound_mailbox_0.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
outbound_mailbox_0.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
outbound_mailbox_0.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
outbound_mailbox_0.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
outbound_mailbox_0.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
outbound_mailbox_0.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
inbound_mailbox_0.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
inbound_mailbox_0.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
inbound_mailbox_0.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
inbound_mailbox_0.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
inbound_mailbox_0.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
inbound_mailbox_0.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
inbound_mailbox_0.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
inbound_mailbox_0.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
inbound_mailbox_0.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
inbound_mailbox_0.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
outbound_mailbox_1.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
outbound_mailbox_1.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
outbound_mailbox_1.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
outbound_mailbox_1.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
outbound_mailbox_1.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
outbound_mailbox_1.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
outbound_mailbox_1.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
outbound_mailbox_1.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
outbound_mailbox_1.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
outbound_mailbox_1.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
inbound_mailbox_1.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
inbound_mailbox_1.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
inbound_mailbox_1.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
inbound_mailbox_1.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
inbound_mailbox_1.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
inbound_mailbox_1.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
inbound_mailbox_1.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
inbound_mailbox_1.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
inbound_mailbox_1.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
inbound_mailbox_1.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
outbound_mailbox_2.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
outbound_mailbox_2.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
outbound_mailbox_2.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
outbound_mailbox_2.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
outbound_mailbox_2.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
outbound_mailbox_2.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
outbound_mailbox_2.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
outbound_mailbox_2.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
outbound_mailbox_2.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
outbound_mailbox_2.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
inbound_mailbox_2.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
inbound_mailbox_2.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
inbound_mailbox_2.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
inbound_mailbox_2.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
inbound_mailbox_2.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
inbound_mailbox_2.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
inbound_mailbox_2.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
inbound_mailbox_2.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
inbound_mailbox_2.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
inbound_mailbox_2.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
outbound_mailbox_3.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
outbound_mailbox_3.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
outbound_mailbox_3.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
outbound_mailbox_3.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
outbound_mailbox_3.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
outbound_mailbox_3.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
outbound_mailbox_3.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
outbound_mailbox_3.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
outbound_mailbox_3.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
outbound_mailbox_3.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
inbound_mailbox_3.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
inbound_mailbox_3.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
inbound_mailbox_3.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
inbound_mailbox_3.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
inbound_mailbox_3.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
inbound_mailbox_3.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
inbound_mailbox_3.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
inbound_mailbox_3.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
inbound_mailbox_3.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
inbound_mailbox_3.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
outbound_mailbox_4.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
outbound_mailbox_4.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
outbound_mailbox_4.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
outbound_mailbox_4.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
outbound_mailbox_4.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
outbound_mailbox_4.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
outbound_mailbox_4.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
outbound_mailbox_4.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
outbound_mailbox_4.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
outbound_mailbox_4.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
inbound_mailbox_4.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
inbound_mailbox_4.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
inbound_mailbox_4.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
inbound_mailbox_4.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
inbound_mailbox_4.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
inbound_mailbox_4.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
inbound_mailbox_4.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
inbound_mailbox_4.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
inbound_mailbox_4.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
inbound_mailbox_4.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
outbound_mailbox_5.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
outbound_mailbox_5.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
outbound_mailbox_5.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
outbound_mailbox_5.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
outbound_mailbox_5.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
outbound_mailbox_5.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
outbound_mailbox_5.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
outbound_mailbox_5.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
outbound_mailbox_5.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
outbound_mailbox_5.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
inbound_mailbox_5.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
inbound_mailbox_5.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
inbound_mailbox_5.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
inbound_mailbox_5.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
inbound_mailbox_5.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
inbound_mailbox_5.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
inbound_mailbox_5.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
inbound_mailbox_5.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
inbound_mailbox_5.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
inbound_mailbox_5.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
outbound_mailbox_6.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
outbound_mailbox_6.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
outbound_mailbox_6.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
outbound_mailbox_6.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
outbound_mailbox_6.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
outbound_mailbox_6.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
outbound_mailbox_6.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
outbound_mailbox_6.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
outbound_mailbox_6.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
outbound_mailbox_6.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
inbound_mailbox_6.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
inbound_mailbox_6.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
inbound_mailbox_6.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
inbound_mailbox_6.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
inbound_mailbox_6.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
inbound_mailbox_6.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
inbound_mailbox_6.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
inbound_mailbox_6.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
inbound_mailbox_6.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
inbound_mailbox_6.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
outbound_mailbox_7.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
outbound_mailbox_7.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
outbound_mailbox_7.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
outbound_mailbox_7.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
outbound_mailbox_7.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
outbound_mailbox_7.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
outbound_mailbox_7.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
outbound_mailbox_7.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
outbound_mailbox_7.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
outbound_mailbox_7.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
inbound_mailbox_7.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
inbound_mailbox_7.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
inbound_mailbox_7.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
inbound_mailbox_7.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
inbound_mailbox_7.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
inbound_mailbox_7.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
inbound_mailbox_7.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
inbound_mailbox_7.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
inbound_mailbox_7.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
inbound_mailbox_7.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
outbound_mailbox_8.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
outbound_mailbox_8.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
outbound_mailbox_8.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
outbound_mailbox_8.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
outbound_mailbox_8.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
outbound_mailbox_8.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
outbound_mailbox_8.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
outbound_mailbox_8.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
outbound_mailbox_8.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
outbound_mailbox_8.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
inbound_mailbox_8.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
inbound_mailbox_8.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
inbound_mailbox_8.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
inbound_mailbox_8.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
inbound_mailbox_8.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
inbound_mailbox_8.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
inbound_mailbox_8.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
inbound_mailbox_8.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
inbound_mailbox_8.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
inbound_mailbox_8.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
outbound_mailbox_9.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
outbound_mailbox_9.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
outbound_mailbox_9.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
outbound_mailbox_9.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
outbound_mailbox_9.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
outbound_mailbox_9.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
outbound_mailbox_9.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
outbound_mailbox_9.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
outbound_mailbox_9.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
outbound_mailbox_9.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
inbound_mailbox_9.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
inbound_mailbox_9.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
inbound_mailbox_9.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
inbound_mailbox_9.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
inbound_mailbox_9.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
inbound_mailbox_9.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
inbound_mailbox_9.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
inbound_mailbox_9.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
inbound_mailbox_9.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
inbound_mailbox_9.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
outbound_mailbox_10.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
outbound_mailbox_10.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
outbound_mailbox_10.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
outbound_mailbox_10.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
outbound_mailbox_10.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
outbound_mailbox_10.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
outbound_mailbox_10.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
outbound_mailbox_10.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
outbound_mailbox_10.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
outbound_mailbox_10.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
inbound_mailbox_10.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
inbound_mailbox_10.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
inbound_mailbox_10.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
inbound_mailbox_10.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
inbound_mailbox_10.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
inbound_mailbox_10.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
inbound_mailbox_10.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
inbound_mailbox_10.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
inbound_mailbox_10.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
inbound_mailbox_10.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
outbound_mailbox_11.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
outbound_mailbox_11.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
outbound_mailbox_11.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
outbound_mailbox_11.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
outbound_mailbox_11.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
outbound_mailbox_11.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
outbound_mailbox_11.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
outbound_mailbox_11.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
outbound_mailbox_11.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
outbound_mailbox_11.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
inbound_mailbox_11.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
inbound_mailbox_11.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
inbound_mailbox_11.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
inbound_mailbox_11.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
inbound_mailbox_11.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
inbound_mailbox_11.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
inbound_mailbox_11.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
inbound_mailbox_11.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
inbound_mailbox_11.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
inbound_mailbox_11.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
outbound_mailbox_12.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
outbound_mailbox_12.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
outbound_mailbox_12.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
outbound_mailbox_12.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
outbound_mailbox_12.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
outbound_mailbox_12.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
outbound_mailbox_12.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
outbound_mailbox_12.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
outbound_mailbox_12.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
outbound_mailbox_12.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
inbound_mailbox_12.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
inbound_mailbox_12.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
inbound_mailbox_12.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
inbound_mailbox_12.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
inbound_mailbox_12.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
inbound_mailbox_12.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
inbound_mailbox_12.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
inbound_mailbox_12.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
inbound_mailbox_12.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
inbound_mailbox_12.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
outbound_mailbox_13.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
outbound_mailbox_13.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
outbound_mailbox_13.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
outbound_mailbox_13.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
outbound_mailbox_13.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
outbound_mailbox_13.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
outbound_mailbox_13.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
outbound_mailbox_13.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
outbound_mailbox_13.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
outbound_mailbox_13.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
inbound_mailbox_13.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
inbound_mailbox_13.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
inbound_mailbox_13.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
inbound_mailbox_13.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
inbound_mailbox_13.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
inbound_mailbox_13.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
inbound_mailbox_13.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
inbound_mailbox_13.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
inbound_mailbox_13.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
inbound_mailbox_13.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
outbound_mailbox_14.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
outbound_mailbox_14.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
outbound_mailbox_14.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
outbound_mailbox_14.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
outbound_mailbox_14.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
outbound_mailbox_14.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
outbound_mailbox_14.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
outbound_mailbox_14.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
outbound_mailbox_14.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
outbound_mailbox_14.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
inbound_mailbox_14.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
inbound_mailbox_14.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
inbound_mailbox_14.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
inbound_mailbox_14.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
inbound_mailbox_14.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
inbound_mailbox_14.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
inbound_mailbox_14.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
inbound_mailbox_14.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
inbound_mailbox_14.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
inbound_mailbox_14.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
outbound_mailbox_15.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
outbound_mailbox_15.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
outbound_mailbox_15.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
outbound_mailbox_15.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
outbound_mailbox_15.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
outbound_mailbox_15.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
outbound_mailbox_15.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
outbound_mailbox_15.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
outbound_mailbox_15.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
outbound_mailbox_15.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
inbound_mailbox_15.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
inbound_mailbox_15.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
inbound_mailbox_15.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
inbound_mailbox_15.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
inbound_mailbox_15.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
inbound_mailbox_15.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
inbound_mailbox_15.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
inbound_mailbox_15.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
inbound_mailbox_15.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
inbound_mailbox_15.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
outbound_mailbox_16.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
outbound_mailbox_16.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
outbound_mailbox_16.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
outbound_mailbox_16.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
outbound_mailbox_16.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
outbound_mailbox_16.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
outbound_mailbox_16.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
outbound_mailbox_16.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
outbound_mailbox_16.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
outbound_mailbox_16.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
inbound_mailbox_16.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
inbound_mailbox_16.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
inbound_mailbox_16.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
inbound_mailbox_16.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
inbound_mailbox_16.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
inbound_mailbox_16.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
inbound_mailbox_16.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
inbound_mailbox_16.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
inbound_mailbox_16.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
inbound_mailbox_16.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
outbound_mailbox_17.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
outbound_mailbox_17.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
outbound_mailbox_17.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
outbound_mailbox_17.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
outbound_mailbox_17.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
outbound_mailbox_17.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
outbound_mailbox_17.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
outbound_mailbox_17.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
outbound_mailbox_17.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
outbound_mailbox_17.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
inbound_mailbox_17.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
inbound_mailbox_17.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
inbound_mailbox_17.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
inbound_mailbox_17.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
inbound_mailbox_17.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
inbound_mailbox_17.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
inbound_mailbox_17.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
inbound_mailbox_17.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
inbound_mailbox_17.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
inbound_mailbox_17.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
outbound_mailbox_18.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
outbound_mailbox_18.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
outbound_mailbox_18.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
outbound_mailbox_18.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
outbound_mailbox_18.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
outbound_mailbox_18.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
outbound_mailbox_18.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
outbound_mailbox_18.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
outbound_mailbox_18.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
outbound_mailbox_18.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
inbound_mailbox_18.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
inbound_mailbox_18.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
inbound_mailbox_18.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
inbound_mailbox_18.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
inbound_mailbox_18.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
inbound_mailbox_18.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
inbound_mailbox_18.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
inbound_mailbox_18.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
inbound_mailbox_18.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
inbound_mailbox_18.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
outbound_mailbox_19.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
outbound_mailbox_19.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
outbound_mailbox_19.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
outbound_mailbox_19.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
outbound_mailbox_19.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
outbound_mailbox_19.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
outbound_mailbox_19.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
outbound_mailbox_19.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
outbound_mailbox_19.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
outbound_mailbox_19.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
inbound_mailbox_19.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
inbound_mailbox_19.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
inbound_mailbox_19.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
inbound_mailbox_19.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
inbound_mailbox_19.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
inbound_mailbox_19.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
inbound_mailbox_19.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
inbound_mailbox_19.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
inbound_mailbox_19.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
inbound_mailbox_19.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
outbound_mailbox_20.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
outbound_mailbox_20.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
outbound_mailbox_20.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
outbound_mailbox_20.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
outbound_mailbox_20.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
outbound_mailbox_20.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
outbound_mailbox_20.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
outbound_mailbox_20.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
outbound_mailbox_20.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
outbound_mailbox_20.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
inbound_mailbox_20.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
inbound_mailbox_20.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
inbound_mailbox_20.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
inbound_mailbox_20.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
inbound_mailbox_20.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
inbound_mailbox_20.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
inbound_mailbox_20.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
inbound_mailbox_20.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
inbound_mailbox_20.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
inbound_mailbox_20.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
outbound_mailbox_21.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
outbound_mailbox_21.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
outbound_mailbox_21.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
outbound_mailbox_21.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
outbound_mailbox_21.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
outbound_mailbox_21.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
outbound_mailbox_21.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
outbound_mailbox_21.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
outbound_mailbox_21.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
outbound_mailbox_21.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
inbound_mailbox_21.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
inbound_mailbox_21.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
inbound_mailbox_21.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
inbound_mailbox_21.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
inbound_mailbox_21.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
inbound_mailbox_21.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
inbound_mailbox_21.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
inbound_mailbox_21.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
inbound_mailbox_21.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
inbound_mailbox_21.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
outbound_mailbox_22.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
outbound_mailbox_22.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
outbound_mailbox_22.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
outbound_mailbox_22.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
outbound_mailbox_22.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
outbound_mailbox_22.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
outbound_mailbox_22.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
outbound_mailbox_22.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
outbound_mailbox_22.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
outbound_mailbox_22.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
inbound_mailbox_22.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
inbound_mailbox_22.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
inbound_mailbox_22.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
inbound_mailbox_22.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
inbound_mailbox_22.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
inbound_mailbox_22.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
inbound_mailbox_22.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
inbound_mailbox_22.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
inbound_mailbox_22.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
inbound_mailbox_22.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
outbound_mailbox_23.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
outbound_mailbox_23.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
outbound_mailbox_23.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
outbound_mailbox_23.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
outbound_mailbox_23.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
outbound_mailbox_23.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
outbound_mailbox_23.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
outbound_mailbox_23.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
outbound_mailbox_23.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
outbound_mailbox_23.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
inbound_mailbox_23.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
inbound_mailbox_23.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
inbound_mailbox_23.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
inbound_mailbox_23.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
inbound_mailbox_23.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
inbound_mailbox_23.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
inbound_mailbox_23.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
inbound_mailbox_23.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
inbound_mailbox_23.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
inbound_mailbox_23.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
outbound_mailbox_24.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
outbound_mailbox_24.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
outbound_mailbox_24.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
outbound_mailbox_24.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
outbound_mailbox_24.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
outbound_mailbox_24.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
outbound_mailbox_24.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
outbound_mailbox_24.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
outbound_mailbox_24.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
outbound_mailbox_24.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
inbound_mailbox_24.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
inbound_mailbox_24.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
inbound_mailbox_24.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
inbound_mailbox_24.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
inbound_mailbox_24.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
inbound_mailbox_24.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
inbound_mailbox_24.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
inbound_mailbox_24.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
inbound_mailbox_24.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
inbound_mailbox_24.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
outbound_mailbox_25.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
outbound_mailbox_25.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
outbound_mailbox_25.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
outbound_mailbox_25.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
outbound_mailbox_25.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
outbound_mailbox_25.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
outbound_mailbox_25.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
outbound_mailbox_25.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
outbound_mailbox_25.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
outbound_mailbox_25.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
inbound_mailbox_25.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
inbound_mailbox_25.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
inbound_mailbox_25.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
inbound_mailbox_25.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
inbound_mailbox_25.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
inbound_mailbox_25.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
inbound_mailbox_25.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
inbound_mailbox_25.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
inbound_mailbox_25.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
inbound_mailbox_25.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
outbound_mailbox_26.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
outbound_mailbox_26.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
outbound_mailbox_26.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
outbound_mailbox_26.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
outbound_mailbox_26.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
outbound_mailbox_26.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
outbound_mailbox_26.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
outbound_mailbox_26.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
outbound_mailbox_26.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
outbound_mailbox_26.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
inbound_mailbox_26.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
inbound_mailbox_26.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
inbound_mailbox_26.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
inbound_mailbox_26.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
inbound_mailbox_26.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
inbound_mailbox_26.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
inbound_mailbox_26.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
inbound_mailbox_26.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
inbound_mailbox_26.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
inbound_mailbox_26.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
outbound_mailbox_27.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
outbound_mailbox_27.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
outbound_mailbox_27.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
outbound_mailbox_27.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
outbound_mailbox_27.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
outbound_mailbox_27.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
outbound_mailbox_27.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
outbound_mailbox_27.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
outbound_mailbox_27.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
outbound_mailbox_27.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
inbound_mailbox_27.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
inbound_mailbox_27.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
inbound_mailbox_27.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
inbound_mailbox_27.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
inbound_mailbox_27.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
inbound_mailbox_27.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
inbound_mailbox_27.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
inbound_mailbox_27.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
inbound_mailbox_27.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
inbound_mailbox_27.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
outbound_mailbox_28.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
outbound_mailbox_28.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
outbound_mailbox_28.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
outbound_mailbox_28.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
outbound_mailbox_28.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
outbound_mailbox_28.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
outbound_mailbox_28.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
outbound_mailbox_28.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
outbound_mailbox_28.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
outbound_mailbox_28.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
inbound_mailbox_28.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
inbound_mailbox_28.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
inbound_mailbox_28.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
inbound_mailbox_28.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
inbound_mailbox_28.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
inbound_mailbox_28.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
inbound_mailbox_28.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
inbound_mailbox_28.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
inbound_mailbox_28.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
inbound_mailbox_28.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
outbound_mailbox_29.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
outbound_mailbox_29.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
outbound_mailbox_29.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
outbound_mailbox_29.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
outbound_mailbox_29.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
outbound_mailbox_29.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
outbound_mailbox_29.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
outbound_mailbox_29.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
outbound_mailbox_29.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
outbound_mailbox_29.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
inbound_mailbox_29.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
inbound_mailbox_29.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
inbound_mailbox_29.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
inbound_mailbox_29.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
inbound_mailbox_29.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
inbound_mailbox_29.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
inbound_mailbox_29.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
inbound_mailbox_29.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
inbound_mailbox_29.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
inbound_mailbox_29.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
outbound_mailbox_30.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
outbound_mailbox_30.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
outbound_mailbox_30.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
outbound_mailbox_30.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
outbound_mailbox_30.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
outbound_mailbox_30.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
outbound_mailbox_30.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
outbound_mailbox_30.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
outbound_mailbox_30.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
outbound_mailbox_30.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
inbound_mailbox_30.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
inbound_mailbox_30.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
inbound_mailbox_30.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
inbound_mailbox_30.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
inbound_mailbox_30.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
inbound_mailbox_30.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
inbound_mailbox_30.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
inbound_mailbox_30.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
inbound_mailbox_30.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
inbound_mailbox_30.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
outbound_mailbox_31.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
outbound_mailbox_31.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
outbound_mailbox_31.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
outbound_mailbox_31.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
outbound_mailbox_31.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
outbound_mailbox_31.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
outbound_mailbox_31.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
outbound_mailbox_31.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
outbound_mailbox_31.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
outbound_mailbox_31.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
inbound_mailbox_31.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
inbound_mailbox_31.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
inbound_mailbox_31.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
inbound_mailbox_31.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
inbound_mailbox_31.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
inbound_mailbox_31.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
inbound_mailbox_31.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
inbound_mailbox_31.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
inbound_mailbox_31.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
inbound_mailbox_31.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
SEP AXI-Lite Mailbox Wrapper Address Map
SEP-side wrapper instantiating the AXI-Lite mailbox pairs.
Each outbound_mailbox_N / inbound_mailbox_N pair is the two apertures of one
bidirectional mailbox and shares a single pair of FIFOs: data written through
WRITE_DATA in one aperture is what READ_DATA in the other aperture returns.
The outbound/inbound naming reflects intended use, not an access restriction.
Register List:
| Address | Name | Access | Description |
|---|---|---|---|
| 0x0 | outbound_mailbox_0.WRITE_DATA | W | - |
| 0x8 | outbound_mailbox_0.READ_DATA | R | - |
| 0x10 | outbound_mailbox_0.STATUS | R | - |
| 0x18 | outbound_mailbox_0.ERROR_FLAGS | R | - |
| 0x20 | outbound_mailbox_0.WIRQT | RW | - |
| 0x28 | outbound_mailbox_0.RIRQT | RW | - |
| 0x30 | outbound_mailbox_0.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x38 | outbound_mailbox_0.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x40 | outbound_mailbox_0.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x48 | outbound_mailbox_0.CTRL | W | - |
| 0x800 | inbound_mailbox_0.WRITE_DATA | W | - |
| 0x808 | inbound_mailbox_0.READ_DATA | R | - |
| 0x810 | inbound_mailbox_0.STATUS | R | - |
| 0x818 | inbound_mailbox_0.ERROR_FLAGS | R | - |
| 0x820 | inbound_mailbox_0.WIRQT | RW | - |
| 0x828 | inbound_mailbox_0.RIRQT | RW | - |
| 0x830 | inbound_mailbox_0.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x838 | inbound_mailbox_0.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x840 | inbound_mailbox_0.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x848 | inbound_mailbox_0.CTRL | W | - |
| 0x1000 | outbound_mailbox_1.WRITE_DATA | W | - |
| 0x1008 | outbound_mailbox_1.READ_DATA | R | - |
| 0x1010 | outbound_mailbox_1.STATUS | R | - |
| 0x1018 | outbound_mailbox_1.ERROR_FLAGS | R | - |
| 0x1020 | outbound_mailbox_1.WIRQT | RW | - |
| 0x1028 | outbound_mailbox_1.RIRQT | RW | - |
| 0x1030 | outbound_mailbox_1.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x1038 | outbound_mailbox_1.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x1040 | outbound_mailbox_1.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x1048 | outbound_mailbox_1.CTRL | W | - |
| 0x1800 | inbound_mailbox_1.WRITE_DATA | W | - |
| 0x1808 | inbound_mailbox_1.READ_DATA | R | - |
| 0x1810 | inbound_mailbox_1.STATUS | R | - |
| 0x1818 | inbound_mailbox_1.ERROR_FLAGS | R | - |
| 0x1820 | inbound_mailbox_1.WIRQT | RW | - |
| 0x1828 | inbound_mailbox_1.RIRQT | RW | - |
| 0x1830 | inbound_mailbox_1.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x1838 | inbound_mailbox_1.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x1840 | inbound_mailbox_1.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x1848 | inbound_mailbox_1.CTRL | W | - |
| 0x2000 | outbound_mailbox_2.WRITE_DATA | W | - |
| 0x2008 | outbound_mailbox_2.READ_DATA | R | - |
| 0x2010 | outbound_mailbox_2.STATUS | R | - |
| 0x2018 | outbound_mailbox_2.ERROR_FLAGS | R | - |
| 0x2020 | outbound_mailbox_2.WIRQT | RW | - |
| 0x2028 | outbound_mailbox_2.RIRQT | RW | - |
| 0x2030 | outbound_mailbox_2.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x2038 | outbound_mailbox_2.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x2040 | outbound_mailbox_2.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x2048 | outbound_mailbox_2.CTRL | W | - |
| 0x2800 | inbound_mailbox_2.WRITE_DATA | W | - |
| 0x2808 | inbound_mailbox_2.READ_DATA | R | - |
| 0x2810 | inbound_mailbox_2.STATUS | R | - |
| 0x2818 | inbound_mailbox_2.ERROR_FLAGS | R | - |
| 0x2820 | inbound_mailbox_2.WIRQT | RW | - |
| 0x2828 | inbound_mailbox_2.RIRQT | RW | - |
| 0x2830 | inbound_mailbox_2.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x2838 | inbound_mailbox_2.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x2840 | inbound_mailbox_2.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x2848 | inbound_mailbox_2.CTRL | W | - |
| 0x3000 | outbound_mailbox_3.WRITE_DATA | W | - |
| 0x3008 | outbound_mailbox_3.READ_DATA | R | - |
| 0x3010 | outbound_mailbox_3.STATUS | R | - |
| 0x3018 | outbound_mailbox_3.ERROR_FLAGS | R | - |
| 0x3020 | outbound_mailbox_3.WIRQT | RW | - |
| 0x3028 | outbound_mailbox_3.RIRQT | RW | - |
| 0x3030 | outbound_mailbox_3.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x3038 | outbound_mailbox_3.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x3040 | outbound_mailbox_3.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x3048 | outbound_mailbox_3.CTRL | W | - |
| 0x3800 | inbound_mailbox_3.WRITE_DATA | W | - |
| 0x3808 | inbound_mailbox_3.READ_DATA | R | - |
| 0x3810 | inbound_mailbox_3.STATUS | R | - |
| 0x3818 | inbound_mailbox_3.ERROR_FLAGS | R | - |
| 0x3820 | inbound_mailbox_3.WIRQT | RW | - |
| 0x3828 | inbound_mailbox_3.RIRQT | RW | - |
| 0x3830 | inbound_mailbox_3.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x3838 | inbound_mailbox_3.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x3840 | inbound_mailbox_3.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x3848 | inbound_mailbox_3.CTRL | W | - |
| 0x4000 | outbound_mailbox_4.WRITE_DATA | W | - |
| 0x4008 | outbound_mailbox_4.READ_DATA | R | - |
| 0x4010 | outbound_mailbox_4.STATUS | R | - |
| 0x4018 | outbound_mailbox_4.ERROR_FLAGS | R | - |
| 0x4020 | outbound_mailbox_4.WIRQT | RW | - |
| 0x4028 | outbound_mailbox_4.RIRQT | RW | - |
| 0x4030 | outbound_mailbox_4.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x4038 | outbound_mailbox_4.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x4040 | outbound_mailbox_4.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x4048 | outbound_mailbox_4.CTRL | W | - |
| 0x4800 | inbound_mailbox_4.WRITE_DATA | W | - |
| 0x4808 | inbound_mailbox_4.READ_DATA | R | - |
| 0x4810 | inbound_mailbox_4.STATUS | R | - |
| 0x4818 | inbound_mailbox_4.ERROR_FLAGS | R | - |
| 0x4820 | inbound_mailbox_4.WIRQT | RW | - |
| 0x4828 | inbound_mailbox_4.RIRQT | RW | - |
| 0x4830 | inbound_mailbox_4.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x4838 | inbound_mailbox_4.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x4840 | inbound_mailbox_4.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x4848 | inbound_mailbox_4.CTRL | W | - |
| 0x5000 | outbound_mailbox_5.WRITE_DATA | W | - |
| 0x5008 | outbound_mailbox_5.READ_DATA | R | - |
| 0x5010 | outbound_mailbox_5.STATUS | R | - |
| 0x5018 | outbound_mailbox_5.ERROR_FLAGS | R | - |
| 0x5020 | outbound_mailbox_5.WIRQT | RW | - |
| 0x5028 | outbound_mailbox_5.RIRQT | RW | - |
| 0x5030 | outbound_mailbox_5.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x5038 | outbound_mailbox_5.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x5040 | outbound_mailbox_5.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x5048 | outbound_mailbox_5.CTRL | W | - |
| 0x5800 | inbound_mailbox_5.WRITE_DATA | W | - |
| 0x5808 | inbound_mailbox_5.READ_DATA | R | - |
| 0x5810 | inbound_mailbox_5.STATUS | R | - |
| 0x5818 | inbound_mailbox_5.ERROR_FLAGS | R | - |
| 0x5820 | inbound_mailbox_5.WIRQT | RW | - |
| 0x5828 | inbound_mailbox_5.RIRQT | RW | - |
| 0x5830 | inbound_mailbox_5.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x5838 | inbound_mailbox_5.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x5840 | inbound_mailbox_5.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x5848 | inbound_mailbox_5.CTRL | W | - |
| 0x6000 | outbound_mailbox_6.WRITE_DATA | W | - |
| 0x6008 | outbound_mailbox_6.READ_DATA | R | - |
| 0x6010 | outbound_mailbox_6.STATUS | R | - |
| 0x6018 | outbound_mailbox_6.ERROR_FLAGS | R | - |
| 0x6020 | outbound_mailbox_6.WIRQT | RW | - |
| 0x6028 | outbound_mailbox_6.RIRQT | RW | - |
| 0x6030 | outbound_mailbox_6.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x6038 | outbound_mailbox_6.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x6040 | outbound_mailbox_6.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x6048 | outbound_mailbox_6.CTRL | W | - |
| 0x6800 | inbound_mailbox_6.WRITE_DATA | W | - |
| 0x6808 | inbound_mailbox_6.READ_DATA | R | - |
| 0x6810 | inbound_mailbox_6.STATUS | R | - |
| 0x6818 | inbound_mailbox_6.ERROR_FLAGS | R | - |
| 0x6820 | inbound_mailbox_6.WIRQT | RW | - |
| 0x6828 | inbound_mailbox_6.RIRQT | RW | - |
| 0x6830 | inbound_mailbox_6.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x6838 | inbound_mailbox_6.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x6840 | inbound_mailbox_6.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x6848 | inbound_mailbox_6.CTRL | W | - |
| 0x7000 | outbound_mailbox_7.WRITE_DATA | W | - |
| 0x7008 | outbound_mailbox_7.READ_DATA | R | - |
| 0x7010 | outbound_mailbox_7.STATUS | R | - |
| 0x7018 | outbound_mailbox_7.ERROR_FLAGS | R | - |
| 0x7020 | outbound_mailbox_7.WIRQT | RW | - |
| 0x7028 | outbound_mailbox_7.RIRQT | RW | - |
| 0x7030 | outbound_mailbox_7.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x7038 | outbound_mailbox_7.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x7040 | outbound_mailbox_7.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x7048 | outbound_mailbox_7.CTRL | W | - |
| 0x7800 | inbound_mailbox_7.WRITE_DATA | W | - |
| 0x7808 | inbound_mailbox_7.READ_DATA | R | - |
| 0x7810 | inbound_mailbox_7.STATUS | R | - |
| 0x7818 | inbound_mailbox_7.ERROR_FLAGS | R | - |
| 0x7820 | inbound_mailbox_7.WIRQT | RW | - |
| 0x7828 | inbound_mailbox_7.RIRQT | RW | - |
| 0x7830 | inbound_mailbox_7.IRQS | RW | This register is used to read and clear interrupt requests, regardless of IRQEN register and whether the interrupt is enabled or disabled. |
| 0x7838 | inbound_mailbox_7.IRQEN | RW | This register is used to enable and disable which interrupts are sent to the CPU. |
| 0x7840 | inbound_mailbox_7.IRQP | R | This register is used to read the current status of the interrupts sent to the CPU. |
| 0x7848 | inbound_mailbox_7.CTRL | W | - |
Register Details:
outbound_mailbox_0.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
outbound_mailbox_0.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
outbound_mailbox_0.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
outbound_mailbox_0.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
outbound_mailbox_0.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
outbound_mailbox_0.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
outbound_mailbox_0.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
outbound_mailbox_0.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
outbound_mailbox_0.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
outbound_mailbox_0.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
inbound_mailbox_0.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
inbound_mailbox_0.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
inbound_mailbox_0.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
inbound_mailbox_0.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
inbound_mailbox_0.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
inbound_mailbox_0.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
inbound_mailbox_0.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
inbound_mailbox_0.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
inbound_mailbox_0.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
inbound_mailbox_0.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
outbound_mailbox_1.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
outbound_mailbox_1.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
outbound_mailbox_1.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
outbound_mailbox_1.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
outbound_mailbox_1.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
outbound_mailbox_1.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
outbound_mailbox_1.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
outbound_mailbox_1.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
outbound_mailbox_1.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
outbound_mailbox_1.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
inbound_mailbox_1.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
inbound_mailbox_1.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
inbound_mailbox_1.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
inbound_mailbox_1.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
inbound_mailbox_1.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
inbound_mailbox_1.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
inbound_mailbox_1.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
inbound_mailbox_1.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
inbound_mailbox_1.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
inbound_mailbox_1.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
outbound_mailbox_2.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
outbound_mailbox_2.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
outbound_mailbox_2.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
outbound_mailbox_2.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
outbound_mailbox_2.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
outbound_mailbox_2.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
outbound_mailbox_2.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
outbound_mailbox_2.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
outbound_mailbox_2.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
outbound_mailbox_2.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
inbound_mailbox_2.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
inbound_mailbox_2.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
inbound_mailbox_2.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
inbound_mailbox_2.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
inbound_mailbox_2.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
inbound_mailbox_2.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
inbound_mailbox_2.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
inbound_mailbox_2.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
inbound_mailbox_2.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
inbound_mailbox_2.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
outbound_mailbox_3.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
outbound_mailbox_3.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
outbound_mailbox_3.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
outbound_mailbox_3.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
outbound_mailbox_3.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
outbound_mailbox_3.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
outbound_mailbox_3.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
outbound_mailbox_3.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
outbound_mailbox_3.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
outbound_mailbox_3.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
inbound_mailbox_3.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
inbound_mailbox_3.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
inbound_mailbox_3.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
inbound_mailbox_3.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
inbound_mailbox_3.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
inbound_mailbox_3.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
inbound_mailbox_3.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
inbound_mailbox_3.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
inbound_mailbox_3.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
inbound_mailbox_3.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
outbound_mailbox_4.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
outbound_mailbox_4.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
outbound_mailbox_4.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
outbound_mailbox_4.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
outbound_mailbox_4.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
outbound_mailbox_4.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
outbound_mailbox_4.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
outbound_mailbox_4.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
outbound_mailbox_4.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
outbound_mailbox_4.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
inbound_mailbox_4.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
inbound_mailbox_4.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
inbound_mailbox_4.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
inbound_mailbox_4.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
inbound_mailbox_4.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
inbound_mailbox_4.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
inbound_mailbox_4.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
inbound_mailbox_4.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
inbound_mailbox_4.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
inbound_mailbox_4.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
outbound_mailbox_5.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
outbound_mailbox_5.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
outbound_mailbox_5.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
outbound_mailbox_5.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
outbound_mailbox_5.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
outbound_mailbox_5.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
outbound_mailbox_5.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
outbound_mailbox_5.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
outbound_mailbox_5.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
outbound_mailbox_5.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
inbound_mailbox_5.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
inbound_mailbox_5.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
inbound_mailbox_5.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
inbound_mailbox_5.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
inbound_mailbox_5.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
inbound_mailbox_5.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
inbound_mailbox_5.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
inbound_mailbox_5.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
inbound_mailbox_5.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
inbound_mailbox_5.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
outbound_mailbox_6.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
outbound_mailbox_6.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
outbound_mailbox_6.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
outbound_mailbox_6.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
outbound_mailbox_6.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
outbound_mailbox_6.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
outbound_mailbox_6.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
outbound_mailbox_6.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
outbound_mailbox_6.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
outbound_mailbox_6.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
inbound_mailbox_6.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
inbound_mailbox_6.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
inbound_mailbox_6.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
inbound_mailbox_6.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
inbound_mailbox_6.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
inbound_mailbox_6.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
inbound_mailbox_6.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
inbound_mailbox_6.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
inbound_mailbox_6.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
inbound_mailbox_6.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
outbound_mailbox_7.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
outbound_mailbox_7.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
outbound_mailbox_7.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
outbound_mailbox_7.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
outbound_mailbox_7.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
outbound_mailbox_7.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
outbound_mailbox_7.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
outbound_mailbox_7.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
outbound_mailbox_7.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
outbound_mailbox_7.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |
inbound_mailbox_7.WRITE_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | write_data | W WMOD | 0x0 | Write data to mailbox fifo |
inbound_mailbox_7.READ_DATA
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | read_data | R RMOD | - | Read data from mailbox fifo |
inbound_mailbox_7.STATUS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:4 | Reserved | - | - | Reserved |
| 3 | read_level_above_thresh | R | 0x0 | If set, read fifo level is higher than threshold set in RIRQT |
| 2 | write_level_above_thresh | R | 0x0 | If set, write fifo level is higher than threshold set in WIRQT |
| 1 | full | R | 0x0 | 0: Space is available to write, 1: Space is not available to write |
| 0 | empty | R | 0x1 | 0: Data is available to read, 1: Data is not available to read |
inbound_mailbox_7.ERROR_FLAGS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | write_error | R RC | 0x0 | Attempted write to a full mailbox |
| 0 | read_error | R RC | 0x0 | Attempted read from an empty mailbox |
inbound_mailbox_7.WIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | wirqt | RW | 0x0 | When the usage pointer of the FIFO connected to the W channel exceeds this value, a write threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the write FIFO is full. |
inbound_mailbox_7.RIRQT
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:0 | rirqt | RW | 0x0 | When the fill pointer of the FIFO connected to the R channel exceeds this value, a read threshold IRQ is triggered and the corresponding STATUS register bit is set. When a value larger than or equal to the MailboxDepth parameter is written to this register, it gets reduced to MailboxDepth - 1 to ensure an IRQ is triggered when the read FIFO is full. |
inbound_mailbox_7.IRQS
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Error on mailbox access On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 1 | rtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in read mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
| 0 | wtirq | RW1C | 0x0 | On read: [0]: No interrupt request [1]: Usage level threshold in write mailbox exceeded On write: [0]: No acknowledge [1]: Acknowledge and clear interrupt request |
inbound_mailbox_7.IRQEN
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | RW | 0x0 | [0]: Error IRQ disabled [1]: Error IRQ enabled |
| 1 | rtirq | RW | 0x0 | [0]: Read threshold IRQ disabled [1]: Read threshold IRQ enabled |
| 0 | wtirq | RW | 0x0 | [0]: Write threshold IRQ disabled [1]: Write threshold IRQ enabled |
inbound_mailbox_7.IRQP
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:3 | Reserved | - | - | Reserved |
| 2 | eirq | R | 0x0 | [0]: No error IRQ pending [1]: Error IRQ pending |
| 1 | rtirq | R | 0x0 | [0]: No read threshold IRQ pending [1]: Read threshold IRQ pending |
| 0 | wtirq | R | 0x0 | [0]: No write threshold IRQ pending [1]: Write threshold IRQ pending |
inbound_mailbox_7.CTRL
| Bits | Field | Access | Reset | Description |
|---|---|---|---|---|
| 63:2 | Reserved | - | - | Reserved |
| 1 | rflush | W WMOD | 0x0 | Flush the read FIFO for this port |
| 0 | wflush | W WMOD | 0x0 | Flush the write FIFO for this port |