GPIO Peripheral

After cold reset, the controller selects output data, transmit enable and receive enable independently. For each field, the first applicable row wins:

The per-field overrides are use_reg_core2pad, use_reg_tx and use_reg_rx. They allow different sources for data and direction. A hardware LSIO request outranks all three overrides; software-forced LSIO does not. lsio_disable gates both forms of LSIO selection.

DATA_CTRL.lsio_enable reports the hardware request after the disable gate: lsio_interface_select_i && !lsio_disable. It does not report a software-forced selection and is not a general pad-owner indicator.

DATA_CTRL.pad2core returns the synchronized input when interface_enable or use_reg_rx selects register readback; otherwise it returns zero. The pad receiver must also be enabled by the selected owner.

The LSIO return path uses the unsynchronized pad input while either LSIO request is active. This return path is independent of the data/direction priority: a software LSIO request can enable readback even when registers own an output field. During cold reset, the LSIO return path also carries the pad input.

The SMC instantiates one gpio controller per pad in u_smc_padring, 65 in all. Figure 2 shows how the controllers are reached and where the shims sit. u_smc_padring sits in u_smc_peripherals beside the peripheral crossbar u_smc_periph_axi_lite_xbar, which receives the peripheral window from the local crossbar u_smc_local_xbar in u_smc_base. The peripheral crossbar sends the GPIO interface window to u_gpio_intf_demux, which decodes one 16-byte slot per pad and answers any other address with DECERR. The LSIO pad map assigns the SPI, UART, I3C, I2C, AVSBus, system-timer, isolate-request, boot-stall and cool-reset functions to fixed pads, and drives the LSIO plane of each controller. The controllers' pad wires leave the SMC; outside it, the adopter’s pad integration places a gpio_shim and a pad macro on each pad, and decodes the smc_external window to give each shim its gpio_ctrl slot; the rest of that window reaches adopter-specific targets. The figure draws pads 0, 1 and 64; the ellipses stand for the pads between them.

The open reference integration, smc_ip_integration, stands in for the adopter side with one prim_pad_shim per pad at fixed electrical settings, and answers the gpio_ctrl range of the smc_external window with DECERR.

The shim selects drive strength, pull settings and input conditioning in this order: hardware LSIO request, CONTROL.config_enable, software-forced LSIO, then parameter defaults. The LSIO requests use the same disable gate as the controller. In register mode, CONTROL supplies drive_strength, pull_enable_n0_scan, pull_select and schmitt_select.

A separate mux selects a secondary hardware function when CONTROL.hw2_ovrd = 1 and force_primary_i = 0. It overrides the primary data and direction path. force_primary_i restores the primary path regardless of the register setting. The integrator must coordinate switching with both hardware functions.

Electrical effects depend on the connected pad implementation. The supplied gpio_model models output drive and receive enable; it does not model drive strength, pull resistors or input conditioning. Do not interpret the drive_strength encoding as a portable current rating.

The input passes through a three-stage synchronizer before interrupt detection. The selected condition is registered on clk_i and gated by DATA_CTRL.interrupt_enable at interrupt_o.

There is no sticky interrupt status or acknowledge register in this block. A level condition must cease, or the interrupt must be disabled, to remove the request. Edge pulses are not stretched; the receiving interrupt controller must capture them. Detection uses the synchronized input, independently of whether register readback is selected.

rst_primary_ni asynchronously resets interface/control registers, the input synchronizer and interrupt state. rst_cold_ni separately forces controller outputs to data 0, TX disabled and RX=INPUT_BY_DEFAULT, and forces the shim’s electrical settings to their parameter defaults. The integration supplies reset timing; these modules do not synchronize reset deassertion internally.

With INPUT_BY_DEFAULT = 1, the shim’s strap latch follows the pad while cold reset is asserted and holds the level when cold reset is released. This is a level-sensitive latch, not a sample taken on a clk_i edge. With the parameter clear, the captured value is zero.

CONTROL.strap_value and captured_strap_o report that captured level. CONTROL.strap_valid reflects INPUT_BY_DEFAULT; it is not a capture-done flag. Read the strap after the system has released cold reset. Primary reset alone does not recapture it.

The interface-bank filter compares all three AXI PROT bits against the configured read or write requirement. Each direction has its own enable. A mismatch is sent to an error responder and completes with DECERR; disabling a filter permits that direction regardless of PROT.

Filtering resets disabled. The stored read and write requirements reset to 3’b001 (secure, privileged data), but apply only when enabled. PROT expresses transaction attributes, not initiator identity: this filter alone does not establish SEP-only access. It protects the interface bank, not the shim’s separate control bank. The GPIO access filtering procedure in the Programmer’s Guide gives the setup and readback requirements.

The LSIO (Low Speed Input/Output) interface enables hardware-controlled GPIO operation for protocol processing.

The GPIO pad interface provides direct connection to external pads with bidirectional capabilities.

The interrupt interface provides event notification capabilities with configurable trigger modes.

The strap-capture output captured_strap_o is a port of gpio_shim, not of gpio; it holds the pad value captured when the cold reset is released.

The controller’s interface bank contains DATA_CTRL, DATA_CTRL_ENABLE and ACCESS_FILTER; the shim’s control bank contains CONTROL. The generated gpio_intf and gpio_ctrl maps in Section 4.2 define their register offsets, and gpio_wrap defines the bank placement within the composite aperture. The enclosing padring determines their system addresses.