JTAG PTAP

Table 1 identifies the PTAP submodules and the conditions under which they are instantiated.

The TAP controller implements the IEEE 1149.1 16-state finite state machine using one-hot encoding. Each state is assigned a unique bit position within a 16-bit vector, enabling direct state detection via single-bit comparisons.

Table 2 lists the one-hot encodings and functions of the sixteen TAP-controller states.

Five consecutive TCK cycles with TMS high bring the state machine to TEST_LOGIC_RESET from any state, as the IEEE 1149.1 state graph defines. A state register value that is not one of the sixteen one-hot encodings also moves to TEST_LOGIC_RESET on the next rising edge of TCK.

Control signals are generated using a split approach. The update and run-test-idle signals are decoded combinationally from the current state as Moore machine outputs. The capture, shift, test-logic-reset and TDO output enable signals are decoded from the current state and registered on the falling edge of TCK, so they are stable before the next rising edge samples data.

The PTAP employs a three-level reset hierarchy to support power-on initialization, JTAG reset, and conditional register preservation.

Table 3 identifies the source and scope of each PTAP reset.

The primary reset jtag_trst_n is formed by AND-gating the power-on reset input with the external TRST signal. This combined reset feeds all JTAG clock domain logic. The TAP controller derives test_logic_reset from the FSM state, which normally resets all registers. When Test Mode Persistence is enabled, the conditional reset chrst_n allows boundary scan and configuration registers to survive TEST_LOGIC_RESET state transitions while in persistence mode.

The PTAP implements an instruction-dependent data register multiplexer. During IR scan operations, the instruction register connects to the scan path. During DR scan operations, the appropriate data register is selected based on the currently decoded instruction. Each test data register has dedicated scan control logic that enables selection only when the corresponding instruction is active and the required feature is enabled.

The scan path supports zero-length bypass through explicit prim_stdmux2 multiplexer cells rather than behavioral multiplexing. This implementation prevents glitches on scan path selectors during instruction transitions.

STAP selection is implemented as a second-level multiplexer. When the 3DCR register’s select bit is asserted, the STAP chain input replaces the TDR multiplexer output. The STAP scan control signals are generated by OR-combining the instruction register and data register scan controls, enabling STAP operation during both IR and DR scan sequences as required by IEEE 1838. The select bit also gates the select, capture, shift and update strobes of the STAP scan interface, so they stay low while the bit is clear.

The TDO output is retimed on the falling edge of TCK as required by IEEE 1149.1 Section 4.5.2. The retiming register ensures that TDO transitions occur at the same clock edge that samples TDI at the receiving device, maintaining timing margins across board-level JTAG chains. For zero-length bypass operation with the TAP_3DCR STAP-select bit clear, the retimer is bypassed using an explicit prim_stdmux2 cell to minimize scan latency. While the bit is set, TDO is retimed under every instruction, ZERO_LENGTH_BYPASS included.

The IDCODE instruction accesses a TDR containing device identification information.

Table 4 defines the identification fields shifted out by IDCODE.

Bits shifted into the IDCODE TDR are ignored. The Programmer’s Guide gives the TDR access sequence for this register.

The DEBUG_CONTROL instruction accesses a TDR defining general control bits for debug and control of the design.

Table 5 defines the clock-stop and debug-control fields of the DEBUG_CONTROL TDR.

The DEBUG_CONTROL TDR captures bits shifted into its R/W fields and ignores those shifted into its RO fields. The Programmer’s Guide gives the TDR access sequence for this register.

The JTAG_CAPS instruction accesses a read-only TDR reporting the DTP version number and general configuration parameters for the DTP.

Table 6 defines the version and configuration fields reported by JTAG_CAPS.

Bits shifted into the JTAG_CAPS TDR are ignored. The Programmer’s Guide gives the TDR access sequence for this register.

All boundary scan and BIST instructions defined in IEEE 1149.1 are optionally supported, but support is not enabled by default. RTL parameters are provided to selectively enable support for each instruction. Any disabled instruction has the same behavior as the BYPASS instruction.

Any boundary scan instruction that selects the BSRs shifts their contents out on TDO. The Programmer’s Guide gives the TDR access sequence for these registers.

The RUNBIST instruction is optionally supported, but support is not enabled by default. An RTL parameter is provided to selectively enable support. Any disabled instruction has the same behavior as the BYPASS instruction.

When the RUNBIST instruction is selected, the iJTAG network is selected as the active scan chain. An iJTAG network control signal indicates that the RUNBIST instruction is active. A designer may also utilize the decoded INST_SELECT signal to trigger the BIST logic for any instructions that they have enabled.

The PTAP adds no Segment Insertion Bit (SIB) or other scan cell to the iJTAG path. TDI is forwarded unchanged to the iJTAG network, and the network’s return is the RUNBIST TDR, so the length and contents of the RUNBIST DR are defined entirely by the iJTAG network attached to the PTAP.

The Programmer’s Guide gives the BIST execution sequence.

In the JTAG Interface Unit, the iJTAG network begins with three SIBs; their bit map and the integrated scan sequence are given in iJTAG Network.

There is optional support for TMP, but support for TMP is disabled by default. An RTL parameter enables support for TMP.

When TMP support is enabled, a TMP controller is included in the PTAP. The TMP controller manages the active-low CH_RESET_N signal. The CH_RESET_N signal is the reset signal for any registers that must retain their state across TLR soft resets, mainly the boundary scan cells. CH_RESET_N asserts whenever the TAP is in the TLR state except when the TMP controller is in the PERSISTENCE_ON state. When the TMP controller is in the PERSISTENCE_ON state, the only events that will assert CH_RESET_N are full power-on-reset (POR) or TRST signal assertion.

When TMP support is disabled, the CLAMP_HOLD, CLAMP_RELEASE, and TMP_STATUS instructions have the same behavior as the BYPASS instruction, and the CH_RESET_N signal always responds to every POR, TRST, or TLR event, i.e. it is an exact copy of the RESET_N signal.

Table 7 defines the bypass-escape and persistence-status bits.

There is optional support for STAP interfaces, and support is enabled by default. An RTL parameter selects the number of STAP interfaces, where a value of 0 disables STAP support.

In order to properly support the IEEE 1838 standard, a chain of STAP interfaces must be inserted at the end of each chiplet’s scan chain. This is done after the IR Select MUX to ensure that both the instruction registers and TDRs from all enabled PTAPs in the scan chain are scannable. As a consequence, the STAPs require dedicated capture, shift, and update control signals that are triggered during both the IR and DR sequences.

The PTAP has a 2-bit 3DCR register that is accessed with the TAP_3DCR instruction. This register provides an option to bypass all STAPs in the scan chain.

Table 8 defines the configuration-hold and STAP-selection bits.

The select bit takes effect at Update-DR of the scan that writes it. A scan that sets it therefore covers only this register, and the STAP chain joins the scan path from the next IR or DR scan onwards. Software sets the select bit in a TAP_3DCR scan of its own before programming any STAP.

When STAP support is disabled, the TAP_3DCR instruction has the same behavior as the BYPASS instruction, and the STAP scan chain cannot be selected.

The PTAP provides support for a configurable number of IEEE 1149.1-compliant reset controls. The IC_RESET TDR is composed of three independently-enabled slices:

Each slice’s struct must contain .ovrd and .val sub-structs of identical width (checked via an elaboration-time assertion in jtag_ptap). Within jtag_ic_reset_reg, the reset-enable and reset-control bits are interleaved in IEEE 1149.1 §17 order: in each port’s pair, reset_enable is nearer TDO and reset_control nearer TDI, so port n occupies TDR bits 2*n+1 and 2*n+2 (Table 9). jtag_ptap packs the three struct slices into that interleaved bus and unpacks the outputs back into structured form. The TDR carries the SMC slice closest to TDI, then SEP, then the external slice, followed by the single reset_hold bit.

The total length is 2 * (NumSmcIcReset + NumSepIcReset + NumExtIcReset) + 1 bits. Each Num*IcReset is half the width of its slice’s struct type, $bits(ic_reset_*_t) / 2, when the matching IC_RESET_*_ENABLE parameter is set, and 0 otherwise.

Table 9 defines the reset-control, reset-enable, and bypass fields in the IC_RESET TDR.

For each of the resets defined in the TDR, the PTAP exposes two logical signals (grouped into the per-slice jtag_*_reset_ctrl_t structs):

The PTAP provides a scan port for an IEEE 1687-2014-compliant hierarchical iJTAG network. The SELECT_IJTAG instruction is always decoded; no configuration parameter removes it. While it is the current instruction, a DR scan selects the iJTAG network and the network return drives TDO.

The PTAP has three per-bridge debug-disable inputs. The JTAG interface unit synchronizes those bits to TCK and presents them here as ready-to-gate signals. Each input is active-high: when it is 1, the corresponding jtag2axi instance blocks AXI transaction generation.

Table 16 maps the three JTAG2AXI bridges to their active-high disable inputs.

The PTAP uses 6-bit instruction encodings. During the capture phase, the least significant bit (closest to TDO) of the instruction register always presents a 1 to the scan chain, and the next least significant bit presents a 0 as specified by the 1149.1 standard, section 7.2.1. All other bits of the instruction register always return 0s.

Table 17 lists the PTAP instruction encodings and associated register lengths.

The length of each variable-length JTAG2AXI register follows from the bridge’s address width, data width and pipeline depth, and for the series data registers from the size last written to *_AXI_SERIES_CTRL. Section 3.15 defines each layout.

NOTE: All instruction encodings not explicitly defined in this table map to the BYPASS instruction.

Packed control and bus types remain bundles at the jtag_ptap boundary; their members are not separate scalar ports.

The parameters and ports of jtag_ptap are listed in jtag_ptap.

The PTAP depends on the following components: