Open Chiplet Atlas Harness (OCAH) Documentation
Open Chiplet Atlas® (OCA®) Harness Documentation
Guides
Starting with OCAH Technical Reference Manual Integrator Guide Programmer's Guide Application Notes
Version
Downloads
Technical Reference Manual (PDF) Integrator Guide (PDF) Programmer's Guide (PDF) Application Notes (PDF)
Datasheets
System Management Unit (PDF) Debug & Test Ports (PDF) Security Processor (PDF) System Management Controller (PDF) AXI-over-UCIe Bridge (PDF)
GitHub Discussions
Tenstorrent

Technical Reference Manual

    • Documentation Overview
      • List of Figures
      • List of Tables
    • OCAH Architecture & Design
      • Platform Overview
      • OCAH Memory Map
      • Power Domains
      • Clock Domains
      • Reset
      • RTL Assertions
    • OCAH Platform Components
      • System Management Unit (SMU)
        • Security Processor (SEP)
          • Overview
          • Threat Model
          • Attack Countermeasures
          • Clocks and Resets
            • SEP Reset Controller
          • CPU
          • Boot ROM
          • Interconnect
          • Interrupts
          • Peripherals
            • Direct Memory Access (DMA)
            • Mailboxes
            • Peripheral Subsystem
            • Serial Peripheral Interface (SPI)
            • Watchdog Timer (WDT)
          • Security and Lifecycle
            • OTP Fuse Controller
            • Token Processing
            • Security Disable
            • Lifecycle Controller
            • Test Mode Entry
          • Cryptographic Subsystem
            • TRNG and DRBG
            • Entropy Source
            • Entropy Pool
            • AES Cipher
            • HMAC-SHA2
            • KMAC-SHA3
            • Adams Bridge (ABR)
            • OTBN PKA Public Key Accelerator
            • Key Manager
              • Architecture
          • Memory Map and Register Reference
        • System Management Controller (SMC)
          • Overview
          • Clocks and Resets
          • CPU
          • Boot ROM
          • Interconnect
          • Interrupts
          • Peripherals
            • Direct Memory Access Engine
            • Zeroer
            • Watchdog Timer (WDT)
            • Mailboxes
            • System Timer OCTS
            • eFuse
            • UART 16550
            • Log Engine
            • I2C
            • I3C
            • AVSBus Controller
            • GPIO
            • Telemetry Receiver
          • Design-for-Debug and CLA
          • eFuse Scan Protection
          • Memory Map and Register Reference
        • Debug & Test Ports (DTP)
          • Overview
          • Clocks and Resets
          • JTAG Operation
          • Cross-Trigger Operation
          • IP Reference
            • JTAG
              • JTAG Interface Unit
              • JTAG PTAP
              • JTAG STAP
            • Cross-Trigger
              • Cross-Trigger Network
              • Cross-Trigger Port
              • Cross-Trigger Matrix
          • Configuration and Reference
      • System Management Network (SMN)
      • AXI-over-UCIe Bridge (AoU)
        • Overview and Features
        • Architecture
        • Interrupts and Errors
        • PPA
        • Appendices
          • Appendix B. Referenced Documents
    • RTL Modules Reference
      • IP
        • AVSBus Controller
        • AXI Alias Remap
        • AXI Filter
        • AXI Hang Detector
        • AXI-Lite Mailbox
        • AXI Window Remap
        • DRBG
        • eFuse
        • Entropy Source
        • GPIO
        • I2C
        • I3C
        • iDMA
        • Key Manager
        • Memory Interface
        • Output Remap
        • Scrambler
        • System Timer
        • Telemetry Receiver
        • Zeroer
        • Cross-Trigger Matrix
        • Cross-Trigger Network
        • Cross-Trigger Port
        • JTAG to AXI
        • JTAG Interface Unit
        • JTAG PTAP
        • JTAG STAP
        • Log Engine
        • UART 16550
        • UART Log Engine Wrapper
        • UART Wrapper
      • Subsystems
        • SEP
        • SMC
        • DTP
        • SMU
        • AXI-over-UCIe
      • Common
        • ocah_prim
        • ocah_prim_generic
        • TL-UL
    • IP Reference
    • Appendices
      • Register Field Access Notation
      • Referenced Documents
  • Application Notes
    • latest
  • Getting Started and Contributing Guide
    • latest
  • Integrator Guide
    • latest
  • Open Chiplet Atlas (OCA) Harness
    • latest
  • Programmer's Guide
    • latest
  • Technical Reference Manual
    • latest
  • Guides
  • Technical Reference Manual
  • RTL Modules Reference
  • Common
  • ocah_prim_generic

ocah_prim_generic

Parsed from the RTL.

  • prim_and3

  • prim_ao222

  • prim_clock_nand2

  • prim_flop_3sync

  • prim_flop_3sync_r

  • prim_flop_3sync_s

  • prim_flop_4sync

  • prim_flop_4sync_r

  • prim_flop_4sync_s

  • prim_latch_n

  • prim_metastab_hardened_dffr

  • prim_nand4

  • prim_nor4

  • prim_or2

  • prim_or4

  • prim_stdmux2

ocah_prim TL-UL
Open Chiplet Atlas

The Open Chiplet Atlas® has been developed by Tenstorrent as an open standard.

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