prim_clock_nand2
NAND two inputs for clock-network use.
Drive y_o with ~(a1_i & a2_i). A synthesis build replaces this behavioural model with a clock-capable technology NAND2 cell of the same name and ports.
Ports
| Name | Direction | Type | Description |
|---|---|---|---|
a1_i | input | | First NAND input. |
a2_i | input | | Second NAND input. |
y_o | output | | NAND of a1_i and a2_i. |