CPU

Table 1 summarizes the processor configuration.

Table 2 lists the memory geometry in the generated cluster and the associated macro controls.

The sizes and associativity above are set by the Chipyard configuration and its generated memory interfaces. Changing them requires a matching generated cluster and memory implementation. The *_cfg signals configure the external memory macros; they are passed unchanged to each macro and do not resize caches or the scratchpad. Macro-specific repair and power controls depend on the selected memory implementation.

The cluster uses TileLink internally for the scratchpad and boot ROM, for the PLIC, CLINT and BEUs on the control bus, and for watchdog timers on the peripheral bus. At its boundary, the MMIO manager bridge converts TileLink to AXI4; the L2 frontend bridge converts incoming AXI4 to TileLink. The front-port branch serving cpu_ctrl uses AXI4-Lite. Both AXI4 ports connect to the SMC Fabric.

CPU_CTRL.RESET_CTRL provides per-core reset controls and reset-pulse requests, plus separate uncore and debug-module reset controls. Each core has a 56-bit RESET_VECTOR register, reset to the boot ROM base 0xC004_0000. The wrapper supplies these values to the generated cluster. While warm reset is asserted, it selects 0xC004_0000 instead of the programmed vectors.

Individual core reset clears the core’s private L1 cache and TileLink client state without resetting the shared coherence manager. The current SMC Rocket integration provides no reset-aware coherence mechanism to drain outstanding transactions or preserve dirty cache data. The AXI boundary drain described below does not remove this limitation.

The scratchpad zero-fill sequencer starts when its memory-initialization reset releases. It writes zeros across the scratchpad banks and holds the cores in reset until initialization completes. smc_disable_sram_auto_init_i bypasses this operation. smc_init_mem_done_o reports either completion or bypass; it does not certify memory repair, MBIST success or initialized contents when zero-fill is skipped. The integrator must provide suitable memory contents and ECC state before use when bypassing initialization.

Memory repair and memory built-in self-test (MBIST) are external DFT responsibilities. The external repair controller applies redundant memory elements as required by the selected SRAM implementation. The SMC fuse map provides no repair-data storage; the integrator supplies the repair data and its storage location.

The intended cold-boot sequence is fuse sensing, external repair, then MBIST before normal CPU use. SMC supplies the following sequencing and status interfaces; it does not implement the external repair algorithm.

The ROM checks repair status during early startup, before normal stack use. It treats a clear mem_repair_done as repair not required rather than waiting for completion. When repair reports done, the ROM checks success; the SMC_CONFIG DFT-ignore-error setting can permit boot to continue after a reported failure. These firmware checks do not establish that repair has completed successfully. The external sequencer must enforce the platform’s repair and MBIST requirements before reporting boot-sequence completion.

Table 3 identifies the protocols and roles of the CPU cluster interfaces.

The cluster is reset independently of the surrounding SMC fabric. If the cluster were reset while a transaction on one of its AXI ports was still in flight, the fabric on the other side would be left waiting on a response that never returns, hanging the bus, and could sample boundary signals while they glitch through reset. To avoid this, each AXI port is wrapped in an axi_isolate block that drains the outstanding transactions and holds the boundary at safe values before the reset is allowed to take effect.

Two instances wrap the AXI ports listed above, each sized for up to four outstanding transactions:

The non-AXI status crossings (wb_pc_valid, wb_reg_pc, and the per-core wdt_reset) are clamped to constants over the same window so they cannot leak glitches either. The boundary also self-isolates on cold boot, releasing four cycles after SRAM initialization completes and the cores and uncore are out of reset.

The boundary is shared by all cores and stays isolated while any core or the uncore is in reset. Holding one core in reset therefore also terminates the other cores' MMIO accesses with SLVERR and stalls L2 frontend traffic until every core is released.

All interrupt wiring—MMIO bases for PLIC, CLINT, watchdog, and bus-error units; the authoritative cpu_interrupts_o map; PLIC/CLINT register documentation; and BEU direct interrupt delivery—is documented in Interrupts.

Each core has a watchdog. See Watchdog Timers for operation and the register reference.

Each core has a Bus Error Unit (BEU) at 0xC801_0000 + N * 0x1000, for N = 0 through 3. It reports errors seen by that core’s L1 caches:

An error response from the SMC fabric reaches the BEU only as a cache bus error; the BEU does not distinguish decode, slave or timeout errors. It is not a general AXI transaction monitor and has no independent AXI timeout detector or transaction-data log.

ENABLE selects events that capture CAUSE and PHYS_ADDR while CAUSE is zero. Instruction-cache correctable errors capture a physical address of zero. The register named ACCRUED_ENABLE is instead sticky event status: events accumulate independently of ENABLE, and ordinary software writes replace the bits. PLIC_ENABLE and LOCAL_ENABLE select from that accrued status for the PLIC and direct-core interrupt paths. Capture the diagnostic state before clearing status or rearming cause capture. The generated register map below lists the implemented fields. Delivery and clearing are described in Bus Error Units.

The generated memory map below describes the hart-facing Debug Module memory region. Only the harts of the CPU cluster reach it, over the cluster’s own control bus. The SMC fabric does not route it, so system, SEP and other SMC initiators receive DECERR at every address in the region. Debugger-facing registers such as dmcontrol, dmstatus, abstractcs and sbcs are accessed through the Debug Module Interface (DMI), not through that memory region. Section 10.1 describes them.

JTAG reaches the cluster’s debug transport module and debug module. The configured debug facilities provide per-core register access, program-buffer execution, breakpoints and system bus access. Debug system bus transactions enter through fbus and use the cluster’s interconnect and reset/isolation conditions.

Debug-module reset is separately controlled by CPU_CTRL.RESET_CTRL; its reset value holds the debug module in reset. Separate control does not make debug memory accesses independent of cluster reset or boundary isolation. Per-core boot addresses are controlled by the RESET_VECTOR registers described above.