AoU PPA

Performance evaluation is conducted in both 512-bit local die and 512-bit remote die environments. The initial latency is measured from the AXI input of the local AOU_CORE to the AXI output of the remote AOU_CORE.

Table 1 lists the measured latency of each AXI channel in a back-to-back connection.

The reason of two additional latency for AW and W CH is from WLAST signal generator, and data width converter.

Figure 1 shows the initial transfer latency when AOU_CORE is connected through UCIe.

Figure 2 shows how bandwidth efficiency varies with UCIe FDI latency.

The results of efficiency measurements for read and write operations with varying burst lengths are presented. For write operations, two cases were evaluated. Normal Write and Write Full, where no write strobe bits are transmitted. The measured values and the corresponding expected values are as follows.

Table 2 compares measured and expected efficiency across burst lengths and write modes.

TBD

Figure 3 shows the area contribution of each submodule in a single-resource-plane AoU.

The area for each 1 RP AOU submodule is shown in the figure above.

Among them, the RX_W_FIFO and RX_R_FIFO, which store write data and read data respectively, occupy the largest portion of the AOU area. These FIFOs are currently implemented as register-based FIFOs.

FIFO Depths : TX = 2 entries / RX = 88 entries for R/W data, and 44 entries for AW/AR/B. The 88-entry default for R/W data applies when FDI_CONFIG selects a non-1024b interface; the 1024b configurations (FDI_CFG_SP_128B / FDI_CFG_TP_64B_128B) default to 140 entries, which proportionally increases the R/W FIFO area component. The Expected R/W data for 128GBs/s is 176 entries.

v0.4 AOU_CORE

With 2 RP, each AXI bandwidth is 512 bit and 256 bit, AOU_CORE area was 197k um^2.

The FIFO depth of the two RPs are identical.

Table 3 compares the reported area across resource-plane configurations.