prim_metastab_hardened_dffr
Register d_i in a metastability-hardened flop with async reset to 0.
Behave as a positive-edge D flip-flop with async active-low reset to 0. A synthesis build replaces this behavioural model with a metastability-hardened technology cell of the same name and ports.
Ports
| Name | Direction | Type | Description |
|---|---|---|---|
clk_i | input | | Sampling clock. |
d_i | input | | Data input. |
rst_ni | input | | Async active-low reset; clears q_o to 0. |
q_o | output | | Registered data. |