prim_flop_4sync_r

Synchronize d_i into the clk_i domain through 4 flops.

Chain 4 positive-edge flops so q_o is d_i delayed by four clk_i cycles. Async active-low rst_ni clears the chain to 0.

Ports

Table 1. Ports
Name	Direction	Description
`clk_i`	input	Destination-domain clock.
`d_i`	input	Async data to synchronize.
`rst_ni`	input	Async active-low reset; clears q_o to 0.
`q_o`	output	Synchronized data.