prim_flop_3sync_s
Synchronize d_i into the clk_i domain through 3 flops, with q_o async-set to 1.
Invert d_i, pass it through 3 flops that clear to 0 when set_ni is low, then reinvert so q_o is 1 during and after async set and follows d_i three clk_i cycles later. Use this when the idle or reset value of the destination signal must be high.
Ports
| Name | Direction | Type | Description |
|---|---|---|---|
clk_i | input | | Destination-domain clock. |
d_i | | Async data to synchronize. | |
set_ni | | Async active-low set; forces q_o to 1. | |
q_o | output | | Synchronized data. |