prim_flop_4sync
Synchronize d_i into the clk_i domain through 4 flops.
Chain 4 positive-edge flops so q_o is d_i delayed by four clk_i cycles. The chain has no reset, so q_o is undefined until four clk_i edges after power-up.
Ports
| Name | Direction | Type | Description |
|---|---|---|---|
clk_i | input | | Destination-domain clock. |
d_i | input | | Async data to synchronize. |
q_o | output | | Synchronized data. |