gpio

Drive one GPIO pad from AXI-Lite registers with an LSIO override path.

AXI-Lite accesses pass a gpio_filter AxPROT check before reaching the gpio_intf register block. lsio_interface_select_i steers pad direction and data between register control and the LSIO plane. Each of core2pad data, output enable and input enable is owned, in priority order, by the LSIO pin select, the register override, then the DATA_CTRL.lsio_select software select; DATA_CTRL.lsio_disable blocks both LSIO selects. The pad input is synchronized into clk_i by prim_sync3r for the register readback and the interrupt, which DATA_CTRL.interrupt_type selects as active-high level, active-low level, rising edge or falling edge. GPIO control-register access for the pad ring lives elsewhere; this block handles its own interface registers only. core2pad_* and pad2core_* are the pad-facing request wires.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`MAX_TRANS`	`int unsigned`	`32`	Maximum open transactions per channel in the filter demux.
`INPUT_BY_DEFAULT`	`bit`	`1'b1`	pad2core_en_o value during cold reset and when no source owns the input enable.
`GPIO_INTF_REG_MAP_SIZE`	`bit [AddrWidth-1:0]`	`0`	Interface register-map size in bytes; its clog2 is the address width passed to the register block.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	System clock, rising-edge triggered.
`rst_primary_ni`	input	`logic`	Primary async reset, active-low. Assert asynchronously; deassert synchronously to clk_i. Resets the filter, registers, synchronizer and interrupt state.
`rst_cold_ni`	input	`logic`	Cold reset, active-low, applied combinationally: while low the output is disabled, pad2core_en_o is INPUT_BY_DEFAULT and pad2core_i passes to lsio_pad2core_data_o.
`test_en_i`	input	`logic`	DFT test enable, active-high; drives the filter demux test input.
`axil_req_i`	input	`gpio_axil_req_t`	AXI-Lite CSR request. 32-bit address and data.
`axil_resp_o`	output	`gpio_axil_resp_t`	AXI-Lite CSR response.
`lsio_interface_select_i`	input	`logic`	Active-high LSIO pad-control select; highest priority unless DATA_CTRL.lsio_disable is set.
`lsio_core2pad_en_ni`	input	`logic`	LSIO core-to-pad enable, active-low.
`lsio_core2pad_data_i`	input	`logic`	LSIO core-to-pad data.
`lsio_pad2core_en_ni`	input	`logic`	LSIO pad-to-core enable, active-low.
`lsio_pad2core_data_o`	output	`logic`	Unsynchronized pad2core_i while an LSIO select is active or in cold reset; low otherwise.
`interrupt_o`	output	`logic`	GPIO interrupt, active-high, registered in clk_i and gated by DATA_CTRL.interrupt_enable; a one-cycle pulse in the edge modes.
`core2pad_o`	output		Core-to-pad data.
`core2pad_en_o`	output		Core-to-pad output enable, active-high.
`pad2core_i`	input		Pad-to-core data.
`pad2core_en_o`	output		Pad-to-core input enable, active-high.