avsbus_controller
Bridge AXI-Lite CSR traffic onto an AVSBus V1.3.1 serial link.
AXI-Lite requests reach the register block through axi_lite_to_apb. Command and readback FIFOs cross between the register clock (clk_reg_i) and the AVS clock, which a programmable divider derives from clk_reg_i or clk_ref_i. Release rst_clk_div_ni before the rest of the AVS logic so the generated avs_clock_o is stable before transactions begin. rst_reg_ni is synchronized internally into clk_reg_i, the pre-divider clock and the AVS clock. rst_reg_ni and rst_ref_ni also reset the clock-source mux directly, so each must assert asynchronously and deassert synchronously to its own clock.
Parameters
| Name | Type | Default | Description |
|---|---|---|---|
COMMAND_FIFO_DEPTH | int unsigned | 8 | Depth of the AVS command FIFO. In entries; must be a power of two. Depths of 16 or more can overflow the 4-bit AVS_FIFOS_STATUS slot counts. |
READBACK_FIFO_DEPTH | int unsigned | 8 | Depth of the AVS readback FIFO. In entries; must be a power of two. Depths of 16 or more can overflow the 4-bit AVS_FIFOS_STATUS slot counts. |
Ports
| Name | Direction | Type | Description |
|---|---|---|---|
clk_reg_i | input | logic | Register-domain clock. Also selectable as the AVS clock source. |
clk_ref_i | input | logic | Reference clock. The alternative AVS clock source; the clock-source mux selects it during reset. |
rst_ref_ni | input | logic | Active-low. Async assert; deassert synchronously to clk_ref_i. Resets the clk_ref_i leg of the anti-glitch clock source mux. |
rst_reg_ni | input | logic | Active-low. Async assert; deassert synchronously to clk_reg_i. Resets the clk_reg_i leg of the clock-source mux and, through reset synchronizers, the rest of the controller. |
rst_clk_div_ni | input | logic | Active-low clock-divider reset. Release before the rest of the AVS logic. Asynchronous; resets the programmable clock divider. |
avs_sdata_i | input | logic | AVS slave data in. Serial response from the target device, sampled on the falling edge of the AVS clock. |
avs_mdata_o | output | logic | AVS master data out. Serial command transmission, driven on the rising edge of the AVS clock; high when idle and during reset. |
avs_clock_o | output | logic | AVS serial clock out. The divided AVS clock through a clock gate, closed while idle when STOP_AVS_CLOCK_ON_IDLE is set. |
avs_gpio_enable_o | output | logic | AVS_CONFIG.AVS_GPIO_ENABLE value. Output enable for the avs_clock and avs_mdata pads and input enable for the avs_sdata pad. |
axil_req_i | input | avsbus_controller_pkg::avsbus_axil_req_t | AXI-Lite CSR request. 32-bit address, 32-bit data, 4-bit strobe. |
axil_resp_o | output | avsbus_controller_pkg::avsbus_axil_resp_t | AXI-Lite CSR response. |
interrupt_o | output | logic | Controller interrupt. Level-sensitive, active high; the OR of the unmasked AVS_INTERRUPT bits. |
scan_rst_ni | input | logic | DFT scan reset, active-low. Replaces the synchronized resets while test_en_i is high and resets the clock divider in test mode. |
test_en_i | input | logic | DFT test enable. Active high. Selects clk_test_i, forces the clock source muxes to their test setting and enables the clock-gate test inputs, and selects scan_rst_ni in place of the synchronized resets. |
clk_test_i | input | logic | DFT test clock. Replaces the pre-divider clock while test_en_i is high. |
cur_state_debug_o | output | logic [16:0] | FSM state debug bus. One-hot protocol FSM state, resynchronized from the AVS clock to clk_reg_i. |