efuse_interface_controller

Control eFuse MAP/CTRL/MMR windows, shadow sense, and the fuse-command path to the SHIM.

Arbitrate the functional and JTAG AXI-Lite ports onto one path. Addresses from the MAP base to the MMR end (the CTRL end without HAS_LC_STATE) are bridged to APB and decoded into the MAP, CTRL and MMR windows, with SLVERR for any other address in that span; all other addresses go to the SHIM bank control port. The windows must therefore be ordered MAP, CTRL, MMR.

SEP_SEC_DISABLE_TOKEN is embedded in RTL. HAS_LC_STATE, CLASS1_SHADOW_RANGES, SECRET_SHADOW_RANGES, and LC_STATE_BIT_POSITION configure lifecycle and secret masking.

Sequence sense/program/read through fuse_command_req/resp, with sensing first, then program, then read; apply field locks and token processing, and export shadow_regs_o. ext_boot_seq_done_i gates boot until memory repair / shadow override completes.

Raise locked_field_access_interrupt_o and token_match_fault_o. Debug outputs expose lock, timeout, and token-match state.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`ADDR_WIDTH`	`int unsigned`	`32`	AXI4-Lite address width at the AXI-Lite to APB bridge.
`DATA_WIDTH`	`int unsigned`	`32`	AXI4-Lite data width at the AXI-Lite to APB bridge.
`SEP_SEC_DISABLE_TOKEN`	`bit [255:0]`	`256'b0`	Expected SHA-256 digest of the security-disable token, used by token processing when HAS_LC_STATE is set.
`EFUSE_MAP_REG_MAP_BASE_ADDR`	`bit [31:0]`	`32'h0`	Base address of the MAP window holding the shadow registers.
`EFUSE_MAP_REG_MAP_SIZE`	`bit [31:0]`	`32'h1000`	Size of the MAP window in bytes.
`EfuseMapRegMapEndAddr`	`bit [31:0]`	`EFUSE_MAP_REG_MAP_BASE_ADDR + EFUSE_MAP_REG_MAP_SIZE - 32'd1`	Last byte address of the MAP window.
`EfuseMapRegMapWidth`	`bit [31:0]`	`$clog2(EFUSE_MAP_REG_MAP_SIZE)`	Offset address width of the MAP window.
`EFUSE_CTRL_REG_MAP_BASE_ADDR`	`bit [31:0]`	`32'h1000`	Base address of the CTRL window holding the interface control registers.
`EFUSE_CTRL_REG_MAP_SIZE`	`bit [31:0]`	`32'h1000`	Size of the CTRL window in bytes.
`EfuseCtrlRegMapEndAddr`	`bit [31:0]`	`EFUSE_CTRL_REG_MAP_BASE_ADDR + EFUSE_CTRL_REG_MAP_SIZE - 32'd1`	Last byte address of the CTRL window.
`EFUSE_MMR_REG_MAP_BASE_ADDR`	`bit [31:0]`	`32'h2000`	Base address of the MMR window holding the token registers; decoded only when HAS_LC_STATE is set.
`EFUSE_MMR_REG_MAP_SIZE`	`bit [31:0]`	`32'h1000`	Size of the MMR window in bytes.
`EfuseMmrRegMapEndAddr`	`bit [31:0]`	`EFUSE_MMR_REG_MAP_BASE_ADDR + EFUSE_MMR_REG_MAP_SIZE - 32'd1`	Last byte address of the MMR window.
`SHADOW_REG_BITS`	`int unsigned`	`8192`	Shadow register file size in bits; program and read CSR bit addresses at or above it are rejected as out of bounds.
`ShadowRegBytes`	`int unsigned`	`SHADOW_REG_BITS / 8`	Shadow register file size in bytes.
`EFUSE_MACRO_WORD_WIDTH`	`int unsigned`	`32`	Macro word width in bits.
`EFUSE_FIELDS`	`int unsigned`	`16`	eFuse field-map entry count.
`HAS_LC_STATE`	`bit`	`1'b1`	Set for SEP: adds the MMR window with token processing, the lifecycle state and the RMA token gates; clear for SMC, where MMR accesses return an error.
`CLASS1_SHADOW_RANGES`	`efuse_pkg::shadow_word_range_map_t`	`'0`	Class-1 shadow word ranges, kept in separately named storage for scan exclusion.
`SECRET_SHADOW_RANGES`	`efuse_pkg::shadow_word_range_map_t`	`'0`	Secret shadow ranges masked under secure_tm.
`LcStateWidth`	`int unsigned`	`efuse_pkg::LcStateRawWidth`	Lifecycle-state field width.
`LC_STATE_BIT_POSITION`	`int unsigned`	`0`	Bit address of the lifecycle-state field.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	System clock.
`rst_ni`	input	`logic`	Active-low asynchronous reset.
`axil_req_i`	input	`efuse_axil_req_t`	AXI4-Lite functional-access request.
`axil_resp_o`	output	`efuse_axil_resp_t`	AXI4-Lite functional-access response.
`axil_jtag_req_i`	input	`efuse_axil_req_t`	AXI4-Lite debug-access request from JTAG.
`axil_jtag_resp_o`	output	`efuse_axil_resp_t`	AXI4-Lite debug-access response to JTAG.
`fuse_bank_ctrl_req_o`	output	`efuse_axil_req_t`	AXI4-Lite request to the eFuse bank control registers in the SHIM.
`fuse_bank_ctrl_resp_i`	input	`efuse_axil_resp_t`	AXI4-Lite response from the eFuse bank control registers.
`fuse_command_req_o`	output	`fuse_command_req_t`	Fuse command request to the SHIM after the guard: {address, program data, access_length_words, command, valid}.
`fuse_command_resp_i`	input	`fuse_command_resp_t`	Fuse command response from the SHIM: {read data, command status, valid}.
`secure_tm_i`	input	`logic`	Secure test mode enable, active-high; blocks fuse commands and zeroes the secret shadow words on shadow_regs_o.
`test_en_i`	input	`logic`	DFT test enable.
`scan_rst_ni`	input	`logic`	DFT scan reset, active-low.
`security_disable_i`	input	`logic`	Security disable override, active-high; skips fuse sensing and opens APB access to the shadow registers.
`efuse_field_map_i`	input	`efuse_pkg::rule_t [EFUSE_FIELDS-1:0]`	Per-field access-control rules.
`reset_n_o`	output	`logic`	Active-low reset, released through a synchronizer once fuse sensing and the external boot sequence are done; also resets the program and read interfaces.
`fuse_sense_done_o`	output	`logic`	High once shadow-register loading from the fuses completes.
`security_disable_o`	output	`logic`	Security disable status from token processing; low when HAS_LC_STATE is clear.
`shadow_regs_o`	output	`efuse_map_t`	Shadow register contents; before fuse sensing completes they read as zero, with an invalid lifecycle state when HAS_LC_STATE is set, unless security_disable_o (with HAS_LC_STATE) or security_disable_i (without it) is set.
`ext_boot_seq_done_i`	input	`logic`	External boot sequence complete, such as memory repair and shadow override; gates the release of reset_n_o.
`is_write_locked_shadow_regs_o`	output	`logic`	High during an APB write to the MAP window that a field lock blocks.
`is_read_locked_shadow_regs_o`	output	`logic`	High when the MAP window APB address falls in a read-locked field.
`is_program_locked_o`	output	`logic`	High when the program interface's target bit address is write locked or is an RMA token bit without a token match.
`is_read_locked_o`	output	`logic`	High when the read interface's target bit address falls in a read-locked field.
`is_write_setup_only_o`	output	`logic`	High when the MAP window APB address falls in a set-only field: bits may be set, not cleared.
`is_lc_state_access_o`	output	`logic`	High when the MAP window APB address falls in the lifecycle-state field.
`is_read_timeout_debug_o`	output	`logic`	One-cycle pulse when a read command times out waiting on the SHIM or bank.
`is_program_timeout_debug_o`	output	`logic`	One-cycle pulse when a program command times out waiting on the SHIM or bank.
`is_efuse_req_err_o`	output	`logic`	Sticky guard error set when a lock blocks a program or read; cleared through the CSR efuse_req_error_clear bit.
`is_secure_tm_blocked_o`	output	`logic`	High when fuse traffic is blocked by active secure test mode.
`is_rma_sip_token_match_debug_o`	output	`logic [5:0]`	RMA SiP token match status code; 6'b010101 indicates a match and is tied there when HAS_LC_STATE is clear.
`is_rma_chiplet_token_match_debug_o`	output	`logic [5:0]`	RMA chiplet token match status code; 6'b010101 indicates a match and is tied there when HAS_LC_STATE is clear.
`locked_field_access_interrupt_o`	output	`logic`	High during an APB access to the MAP window that a field lock blocks.
`token_match_fault_o`	output	`logic`	Token comparator redundancy fault, sticky until reset; tied low when HAS_LC_STATE is clear.