ctn_clock_stop_ctrl

OR clock-stop requests and register a glitch-free chiplet halt.

clk_stop_req_i are CLA (or other) requests in the ck_feedthru domain; jtag_clock_stop_i is quasi-static from JTAG_TCK. cla_clock_stop_o is the combinational OR of CLA requests for JTAG status; stop_clks_o passes the OR of those and the JTAG request through a two-flop synchronizer and an output register in clk_i, so it follows the requests after three clk_i cycles.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`NUM_CLK_STOP_REQ`	`int unsigned`	`1`	Number of clock stop request inputs.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	System clock.
`rst_ni`	input	`logic`	Active-low asynchronous reset; clears stop_clks_o.
`clk_stop_req_i`	input	`logic [NUM_CLK_STOP_REQ-1:0]`	Clock-stop requests from individual CLAs or other on-chip sources, active-high and asynchronous to clk_i.
`jtag_clock_stop_i`	input	`logic`	Clock stop from the JTAG DEBUG_CONTROL register, active-high.
`stop_clks_o`	output	`logic`	Registered functional halt in the clk_i domain: the OR of the JTAG and CLA requests, after a two-flop synchronizer. Drives chiplet clock gating.
`cla_clock_stop_o`	output	`logic`	OR of the clk_stop_req_i requests only, for JTAG DEBUG_CONTROL status readback.