log_engine
DMA buffered log bytes to a UART under AXI-Lite CSR control.
The log region is split into NumLogEntries equal slots. Each non-zero LOG_CTRL LOG_LEN requests a transfer from its slot; an arbiter tree serves one entry at a time, and LOG_LEN clears when that transfer completes. log_fetch_axil reads log words from the slot; log_write_axil writes them to LOG_WRITE_ADDR. uart_tx_ready_i paces the writes; irq_o signals fetch or write errors; FIFO_DEPTH sizes the read-data FIFO.
Parameters
| Name | Type | Default | Description |
|---|---|---|---|
FIFO_DEPTH | int unsigned | 4 | Entries in the read-data FIFO between log fetch and UART write. |
Ports
| Name | Direction | Type | Description |
|---|---|---|---|
clk_i | input | logic | System clock, rising-edge triggered. |
rst_ni | input | logic | Active-low reset. Assert asynchronously; deassert synchronously to clk_i. Resets the registers, state machines, counters and the FIFO. |
csr_axil_req_i | input | csr_axil_req_t | Csr AXI-Lite req (AXI4-Lite Register Interface). |
csr_axil_resp_o | output | csr_axil_resp_t | Csr AXI-Lite resp. |
log_fetch_axil_req_o | output | log_fetch_axil_req_t | Log fetch AXI-Lite req (AXI4-Lite Log Fetch Interface). |
log_fetch_axil_resp_i | input | log_fetch_axil_resp_t | Log fetch AXI-Lite resp. |
log_write_axil_req_o | output | log_write_axil_req_t | Log write AXI-Lite req (AXI4-Lite Log Write Interface). |
log_write_axil_resp_i | input | log_write_axil_resp_t | Log write AXI-Lite resp. |
uart_tx_ready_i | input | logic | Uart tx ready, active-high (DMA Interface). The engine writes a log word only while it is high, so the UART TX FIFO never overflows. |
irq_o | output | logic | Interrupt request, active-high. High while any INTR_STATUS bit enabled in INTR_ENABLE is set. |