prim_ag_clk_mux

Mux clk0_i and clk1_i onto clk_o without glitches.

Synchronize sel_i into each source domain, gate the deselected clock off before enabling the other, and combine the gated clocks onto clk_o. SELECT_ON_RESET chooses which clock is enabled while reset is asserted: 0 selects clk0_i during reset, 1 selects clk1_i. test_en_i forces both clock gates open, so clk_o is the OR of clk0_i and clk1_i.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`SELECT_ON_RESET`	`bit`	`1'b0`	0 selects clk0_i during reset; 1 selects clk1_i.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk0_i`	input	`logic`	First clock source.
`clk1_i`	input	`logic`	Second clock source.
`rst_clk0_ni`	input	`logic`	Async active-low reset in the clk0_i domain.
`rst_clk1_ni`	input	`logic`	Async active-low reset in the clk1_i domain.
`test_en_i`	input	`logic`	Scan/test enable; forces both clock gates open.
`sel_i`	input	`logic`	Selects clk1_i when high, clk0_i when low; asynchronous, synchronized into each clock domain through four flops.
`clk_o`	output	`logic`	Glitch-free muxed clock.