prim_apb_arb

Arbitrate MASTER_NUM APB masters onto one slave port.

Register every master's request, pick one with a fair round-robin prim_fair_rr_arb, and replay it on the registered slave port; forward every address without decoding. When SIM_APB_ARB is defined, splice a test master in at the highest index. Grant one master at a time and steer the slave response back to that master through a register stage. Mask the master just served for one cycle after its response so its still-asserted PSEL and PENABLE do not start a second transfer.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`ADDR_WIDTH`	`int unsigned`	`32`	APB address width.
`DATA_WIDTH`	`int unsigned`	`32`	APB data width.
`MASTER_NUM`	`int unsigned`	`8`	Number of APB master ports.
`SLAVE_ADDR_START`	`bit [31:0]`	`32'h0000`	Declared but unused; no address decoding.
`SLAVE_ADDR_END`	`bit [31:0]`	`32'h1000`	Declared but unused; addresses reach the slave port unchecked.
`DataStrbWidth`	`int unsigned`	`DATA_WIDTH / 8`	Write-strobe width from DATA_WIDTH.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	APB clock.
`rst_ni`	input	`logic`	Active-low reset, sampled synchronously; clears requests and controls, while datapath registers are not reset.
`mst_psel_i`	input	`logic [MASTER_NUM-1:0]`	APB master PSELs.
`mst_penable_i`	input	`logic [MASTER_NUM-1:0]`	APB master PENABLEs; a master requests once its PSEL and PENABLE are both high.
`mst_paddr_i`	input	`logic [MASTER_NUM-1:0][ADDR_WIDTH -1:0]`	APB master PADDRs.
`mst_pwrite_i`	input	`logic [MASTER_NUM-1:0]`	APB master PWRITEs.
`mst_pwdata_i`	input	`logic [MASTER_NUM-1:0][DATA_WIDTH -1:0]`	APB master PWDATAs.
`mst_pstrb_i`	input	`logic [MASTER_NUM-1:0][DataStrbWidth -1:0]`	APB master PSTRBs.
`mst_prdata_o`	output	`logic [MASTER_NUM-1:0][DATA_WIDTH -1:0]`	APB master PRDATAs.
`mst_pready_o`	output	`logic [MASTER_NUM-1:0]`	APB master PREADYs.
`mst_pslverr_o`	output	`logic [MASTER_NUM-1:0]`	APB master PSLVERRs.
`slv_psel_o`	output	`logic`	APB slave PSEL.
`slv_penable_o`	output	`logic`	APB slave PENABLE.
`slv_paddr_o`	output	`logic [ADDR_WIDTH -1:0]`	APB slave PADDR.
`slv_pwrite_o`	output	`logic`	APB slave PWRITE.
`slv_pwdata_o`	output	`logic [DATA_WIDTH -1:0]`	APB slave PWDATA.
`slv_pstrb_o`	output	`logic [DataStrbWidth -1:0]`	APB slave PSTRB.
`slv_prdata_i`	input	`logic [DATA_WIDTH -1:0]`	APB slave PRDATA.
`slv_pready_i`	input	`logic`	APB slave PREADY.
`slv_pslverr_i`	input	`logic`	APB slave PSLVERR.