prim_axi_id_converter

Adapt AXI IDs between an upstream and a downstream port of different ID widths.

When AXI_ID_WIDTH_IN exceeds AXI_ID_WIDTH_OUT, remap IDs through axi_id_remap within the MAX_INFLIGHT_IDS and MAX_TXNS_PER_ID limits. When AXI_ID_WIDTH_IN is less than AXI_ID_WIDTH_OUT, zero-extend IDs combinationally through prim_axi_id_prepend_wrap. When the widths are equal, pass requests and responses straight through. test_en_i is not used.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`AXI_ADDR_WIDTH`	`int unsigned`	`64`	Address width of both AXI ports; forwarded to the ID-padding path.
`AXI_DATA_WIDTH`	`int unsigned`	`64`	Data-channel width of both AXI ports; forwarded to the ID-padding path.
`AXI_USER_WIDTH`	`int unsigned`	`1`	User-signal width of both AXI ports; forwarded to the ID-padding path.
`AXI_ID_WIDTH_IN`	`int unsigned`	`16`	Upstream AXI ID width.
`AXI_ID_WIDTH_OUT`	`int unsigned`	`8`	Downstream AXI ID width.
`MAX_INFLIGHT_IDS`	`int unsigned`	`4`	Max distinct upstream IDs in flight; used only by the remap path.
`MAX_TXNS_PER_ID`	`int unsigned`	`4`	Max outstanding transactions per upstream ID; used only by the remap path.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	AXI clock; used only by the remap path.
`rst_ni`	input	`logic`	Async reset, active-low; used only by the remap path.
`test_en_i`	input	`logic`	Not used.
`axi_in_req_i`	input	`input_axi_req_t`	Upstream AXI request.
`axi_in_resp_o`	output	`input_axi_resp_t`	Upstream AXI response.
`axi_out_req_o`	output	`output_axi_req_t`	Downstream AXI request.
`axi_out_resp_i`	input	`output_axi_resp_t`	Downstream AXI response.