prim_axi_id_prepend_wrap

Zero-extend AW and AR IDs from AXI_IN_ID_WIDTH to AXI_OUT_ID_WIDTH on struct AXI ports.

Truncate response IDs back to the upstream width. Pass every non-ID channel field through unchanged; the module is purely combinational. AXI_OUT_ID_WIDTH must be at least AXI_IN_ID_WIDTH, checked by a simulation assertion at time zero.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`AXI_IN_ID_WIDTH`	`int unsigned`	`6`	Upstream AXI ID width.
`AXI_OUT_ID_WIDTH`	`int unsigned`	`8`	Downstream AXI ID width after prepend.
`AXI_DATA_WIDTH`	`int unsigned`	`32`	Data-channel width of both ports; declared but not used.
`AXI_ADDR_WIDTH`	`int unsigned`	`32`	Address width of both ports; declared but not used.
`AXI_USER_WIDTH`	`int unsigned`	`8`	User-signal width of both ports; declared but not used.

Ports

Table 2. Ports
Name	Direction	Type	Description
`axi_in_req_i`	input	`axi_in_req_t`	Upstream AXI request.
`axi_in_resp_o`	output	`axi_in_resp_t`	Upstream AXI response.
`axi_out_req_o`	output	`axi_out_req_t`	Downstream AXI request with wider IDs.
`axi_out_resp_i`	input	`axi_out_resp_t`	Downstream AXI response.