prim_axi_lite_err_slv

Complete every AXI-Lite access with a fixed error response.

RESP and RESP_DATA set the response code and read payload; RESP_DATA is zero-extended or truncated to AXI_DATA_WIDTH for r.data. MAX_TRANS caps accepted outstanding transactions before stalling. Present a struct AXI-Lite slave port over the underlying full-AXI error slave.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`AXI_ADDR_WIDTH`	`int unsigned`	`32`	AXI-Lite address width.
`AXI_DATA_WIDTH`	`int unsigned`	`32`	AXI-Lite data width; a power of two of at least 8.
`RESP`	`axi_pkg::resp_t`	`axi_pkg::RESP_DECERR`	Error response generated by this slave.
`RESP_WIDTH`	`int unsigned`	`32'd64`	Width of RESP_DATA only; r.data is always AXI_DATA_WIDTH wide.
`RESP_DATA`	`logic [RESP_WIDTH-1:0]`	`64'hBADCAB1EBADCAB1E`	Fixed read-data return value.
`MAX_TRANS`	`int unsigned`	`1`	Maximum accepted transactions before stalling.
`AxiStrbWidth`	`int unsigned`	`AXI_DATA_WIDTH / 8`	Write-strobe width; derived.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	AXI-Lite clock.
`rst_ni`	input	`logic`	Async reset, active-low.
`axil_req_i`	input	`axil_req_t`	AXI-Lite request from the manager.
`axil_resp_o`	output	`axil_resp_t`	AXI-Lite error response to the manager.