prim_axi_lite_to_apb_single

Bridge one AXI-Lite manager to a single APB subordinate.

Complete addresses outside [ADDR_START, ADDR_END) with a decode error on AXI-Lite. PIPELINE_REQUEST and PIPELINE_RESPONSE insert skid registers on the request and response paths. Hold only one APB transfer in flight at a time.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`PIPELINE_REQUEST`	`bit`	`1'b0`	Skid-registers the AXI-Lite to APB request path.
`PIPELINE_RESPONSE`	`bit`	`1'b0`	Skid-registers the APB to AXI-Lite response path.
`AXI_DATA_WIDTH`	`int unsigned`	`32`	Shared data width.
`AXI_ADDR_WIDTH`	`int unsigned`	`32`	Shared address width.
`ADDR_START`	`bit [AXI_ADDR_WIDTH-1:0]`	`32'h0`	Inclusive APB decode base.
`ADDR_END`	`bit [AXI_ADDR_WIDTH:0]`	`33'h0`	Exclusive APB decode limit.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	Clock shared by the AXI-Lite and APB sides of the bridge.
`rst_ni`	input	`logic`	Async reset, active-low.
`axi_lite_awvalid_i`	input	`logic`	Write-address valid from the AXI-Lite manager.
`axi_lite_awaddr_i`	input	`addr_t`	Write byte address, decoded against [ADDR_START, ADDR_END).
`axi_lite_awprot_i`	input	`axi_pkg::prot_t`	Write protection attributes, forwarded to pprot_o.
`axi_lite_awready_o`	output	`logic`	Write-address ready to the AXI-Lite manager.
`axi_lite_wvalid_i`	input	`logic`	Write-data valid from the AXI-Lite manager.
`axi_lite_wdata_i`	input	`data_t`	Write data, forwarded to pwdata_o.
`axi_lite_wstrb_i`	input	`strb_t`	Write byte strobes, forwarded to pstrb_o.
`axi_lite_wready_o`	output	`logic`	Write-data ready to the AXI-Lite manager.
`axi_lite_bvalid_o`	output	`logic`	Write-response valid to the AXI-Lite manager.
`axi_lite_bresp_o`	output	`axi_pkg::resp_t`	Write response; SLVERR on pslverr_i, DECERR outside the decode range.
`axi_lite_bready_i`	input	`logic`	Write-response ready from the AXI-Lite manager.
`axi_lite_arvalid_i`	input	`logic`	Read-address valid from the AXI-Lite manager.
`axi_lite_araddr_i`	input	`addr_t`	Read byte address, decoded against [ADDR_START, ADDR_END).
`axi_lite_arprot_i`	input	`axi_pkg::prot_t`	Read protection attributes, forwarded to pprot_o.
`axi_lite_arready_o`	output	`logic`	Read-address ready to the AXI-Lite manager.
`axi_lite_rvalid_o`	output	`logic`	Read-data valid to the AXI-Lite manager.
`axi_lite_rdata_o`	output	`data_t`	Read data returned from prdata_i.
`axi_lite_rresp_o`	output	`axi_pkg::resp_t`	Read response; SLVERR on pslverr_i, DECERR outside the decode range.
`axi_lite_rready_i`	input	`logic`	Read-data ready from the AXI-Lite manager.
`psel_o`	output	`logic`	APB PSEL.
`penable_o`	output	`logic`	APB PENABLE.
`pwrite_o`	output	`logic`	APB PWRITE.
`paddr_o`	output	`addr_t`	APB PADDR.
`pwdata_o`	output	`data_t`	APB PWDATA.
`pstrb_o`	output	`strb_t`	APB PSTRB.
`pprot_o`	output	`logic [2:0]`	APB PPROT.
`pready_i`	input	`logic`	APB PREADY.
`pslverr_i`	input	`logic`	APB PSLVERR.
`prdata_i`	input	`data_t`	APB PRDATA.