prim_axil_access_gate

Answer AXI-Lite accesses with an error response while the subordinate is unavailable.

While block_i is low every request passes to the subordinate port unchanged. While it is high each access completes locally with RESP, reads returning RESP_DATA zero-extended or truncated to DATA_WIDTH, and nothing reaches the subordinate. block_i is sampled when the AW or AR request is accepted, so a request already handed to the subordinate completes there even if block_i rises afterwards. Responses return in request order. clk_i must keep running while block_i is high: the gate sits in front of a subordinate whose own clock may be stopped.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`ADDR_WIDTH`	`int unsigned`	`32`	AXI-Lite address width.
`DATA_WIDTH`	`int unsigned`	`32`	AXI-Lite data width; a power of two of at least 8.
`MAX_TRANS`	`int unsigned`	`1`	Outstanding transactions per channel through the gate.
`RESP`	`axi_pkg::resp_t`	`axi_pkg::RESP_SLVERR`	Response code while blocked.
`RESP_WIDTH`	`int unsigned`	`32'd64`	Width of RESP_DATA only.
`RESP_DATA`	`logic [RESP_WIDTH-1:0]`	`64'hBADCAB1EBADCAB1E`	Read data while blocked.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	AXI-Lite clock; runs while block_i is high.
`rst_ni`	input	`logic`	Async reset, active-low.
`test_en_i`	input	`logic`	DFT/test enable for the internal AXI-Lite demux.
`block_i`	input	`logic`	Answer every newly accepted access with RESP while high.
`axil_req_i`	input	`axil_req_t`	Request from the manager.
`axil_resp_o`	output	`axil_resp_t`	Response toward the manager.
`axil_req_o`	output	`axil_req_t`	Request toward the subordinate.
`axil_resp_i`	input	`axil_resp_t`	Response from the subordinate.