prim_axil_addr_fixer

Widen or truncate AXI-Lite AW and AR addresses between two struct interfaces.

Pass every other AXI-Lite field through unchanged. INPUT_ADDR_W and OUTPUT_ADDR_W set whether the path zero-pads the upper address bits or drops them. The module is purely combinational.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`INPUT_ADDR_W`	`int unsigned`	`64`	Address width on the input AXI-Lite side.
`OUTPUT_ADDR_W`	`int unsigned`	`64`	Address width on the output AXI-Lite side.

Ports

Table 2. Ports
Name	Direction	Type	Description
`axi_in_req_i`	input	`input_axi_req_t`	Upstream AXI-Lite request.
`axi_in_resp_o`	output	`input_axi_resp_t`	Upstream AXI-Lite response.
`axi_out_req_o`	output	`output_axi_req_t`	Downstream AXI-Lite request with fixed address.
`axi_out_resp_i`	input	`output_axi_resp_t`	Downstream AXI-Lite response.