prim_clk_counter

Count clk_i edges while a reference window on refclk_i is open.

Close the window on refclk_cnt_done_i and make clk_cnt_o valid; the counter restarts from zero at each window end and saturates at all ones. test_mode_i swaps scan_rst_ni onto the reset path. cnt_en_i must be high for the counter to run; it crosses from refclk_i to clk_i through a 4-phase handshake, and refclk_cnt_done_i through a toggle pulse synchronizer.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`WIDTH`	`int unsigned`	`24`	Counter width.

Ports

Table 2. Ports
Name	Direction	Type	Description
`refclk_i`	input	`logic`	Reference clock for the measurement window.
`refclk_cnt_done_i`	input	`logic`	Single-cycle pulse on refclk_i that ends each window.
`refclk_rst_ni`	input	`logic`	Active-low reset for the refclk_i-side logic and both CDC source sides.
`clk_i`	input	`logic`	Clock under measurement.
`rst_ni`	input	`logic`	Active-low reset for the clk_i domain; asserts asynchronously, deasserts after four clk_i cycles.
`test_mode_i`	input	`logic`	Selects scan_rst_ni on the reset mux.
`scan_rst_ni`	input	`logic`	DFT scan reset, active-low.
`cnt_en_i`	input	`logic`	Enables counting; in the refclk_i domain. Low clears the count and clk_cnt_valid_o.
`clk_cnt_o`	output	`logic [WIDTH-1:0]`	clk_i cycles counted in the last closed window.
`clk_cnt_valid_o`	output	`logic`	clk_cnt_o is valid after the window closes.