prim_clk_counter_fifo_sync

Measure clk_i against a reference window and return the count through a CDC FIFO.

End the reference window on ref_clk_done_i in the ref_clk_i domain. Arm a measurement with clk_count_en_i. Each change of the counter's valid flag pushes the flag and count through a one-entry async FIFO, and clk_count_valid_o and clk_counts_o hold the last pair received on ss_clk_i. tile_rst_ni resets the clk_i-side counter, either reset clears the FIFO, and ss_rst_ni clears the ss_clk_i output registers.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`CLOCK_COUNTER_WIDTH`	`int unsigned`	`64`	Returned count width.

Ports

Table 2. Ports
Name	Direction	Type	Description
`ref_clk_i`	input	`logic`	Reference clock.
`ref_clk_rst_ni`	input	`logic`	Active-low reset for the ref_clk_i-side logic.
`ref_clk_done_i`	input	`logic`	Single-cycle pulse on ref_clk_i that ends the window.
`tile_rst_ni`	input	`logic`	Active-low reset for the clk_i side; synchronized to clk_i.
`ss_clk_i`	input	`logic`	Read-side clock of the CDC FIFO and output clock.
`ss_rst_ni`	input	`logic`	Active-low reset for the ss_clk_i side; clears the outputs synchronously.
`clk_count_en_i`	input	`logic`	Arms a count; in the ref_clk_i domain.
`clk_i`	input	`logic`	Clock under measurement.
`clk_count_valid_o`	output	`logic`	ss_clk_i copy of the counter's valid flag, updated with clk_counts_o.
`clk_counts_o`	output	`logic [CLOCK_COUNTER_WIDTH-1:0]`	Measured count after CDC, registered on ss_clk_i.