prim_clk_gater_hysteresis

Gate clk_i with a programmable hysteresis after busy_i falls.

Gating happens only while enable_i is high; enable_i low or reset keeps the clock running. kick_i forces an immediate ungating. hysteresis_i is the idle wait in clk_i cycles before gated_clk_o stops. The count reloads on busy_i or kick_i and restarts at all ones after reset. With hysteresis_i all ones a kick is sticky: the countdown waits until busy_i has been seen after the kick. test_clk_en_i forces the clock on for scan.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`HYST_WIDTH`	`int unsigned`	`6`	Width of hysteresis_i.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	Clock to gate.
`rst_ni`	input	`logic`	Active-low reset, sampled synchronously; forces the clock on while low.
`busy_i`	input	`logic`	Reloads the hysteresis count each cycle it is high, keeping the clock running when hysteresis_i is nonzero.
`enable_i`	input	`logic`	Enables clock gating when high; low keeps the clock running.
`kick_i`	input	`logic`	Ungates the clock immediately and reloads the hysteresis count.
`test_clk_en_i`	input	`logic`	Scan force-clock enable.
`hysteresis_i`	input	`logic [HYST_WIDTH-1:0]`	Idle cycles before the gate closes; all ones makes kicks sticky.
`clk_active_o`	output	`logic`	High while the gate is enabled; ignores test_clk_en_i.
`gated_clk_o`	output	`logic`	Gated clock output.