prim_diff_decode_multi

Decode WIDTH differential pairs into single-ended data_o.

Pack data_i as {diff_n[W-1:0], diff_p[W-1:0]}; matching levels assert a per-bit integrity fault. OR every per-bit integrity fault onto sigint_o. ASYNC_ON inserts two-flop synchronizers on the differential inputs into clk_i and tolerates a one-cycle skew between the wires of a pair before flagging a fault. Without ASYNC_ON the decode is combinational: data_o follows diff_p and clk_i and rst_ni are unused.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`WIDTH`	`int unsigned`	`4`	Number of differential pairs.
`ASYNC_ON`	`bit`	`1'b0`	Synchronizes data_i into clk_i when set.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	Decode clock; used only when ASYNC_ON is set.
`rst_ni`	input	`logic`	Async reset, active-low; used only when ASYNC_ON is set.
`data_i`	input	`logic [2*WIDTH-1:0]`	Packed {diff_n[W-1:0], diff_p[W-1:0]}.
`data_o`	output	`logic [WIDTH-1:0]`	Decoded single-ended levels.
`sigint_o`	output	`logic`	OR of all per-bit integrity errors.