prim_diff_encode_multi

Encode WIDTH bits onto differential {diff_n, diff_p} pairs.

Pack data_o as {diff_n[W-1:0], diff_p[W-1:0]} for each bit of data_i. OUTPUT_FLOP registers the pairs on clk_i when set; rst_ni resets each registered pair to the encoding of 0, diff_p low and diff_n high. Without OUTPUT_FLOP the encode is combinational.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`WIDTH`	`int unsigned`	`4`	Number of bits to encode.
`OUTPUT_FLOP`	`bit`	`1'b0`	Registers data_o on clk_i when set.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	Encode clock when OUTPUT_FLOP is set.
`rst_ni`	input	`logic`	Async reset, active-low; used only when OUTPUT_FLOP is set.
`data_i`	input	`logic [WIDTH-1:0]`	Single-ended bits to encode.
`data_o`	output	`logic [2*WIDTH-1:0]`	Packed {diff_n[W-1:0], diff_p[W-1:0]}.