prim_fifo_sync_parity

Store WIDTH-bit beats in a synchronous FIFO with optional pass-through and pointer hardening.

PASS forwards a write into an empty FIFO in the same cycle when set. OUTPUT_ZERO_IF_EMPTY forces rdata_o to zero when the FIFO is empty. SECURE replaces pointer math with prim_count, stores an odd parity bit with each entry and checks it on read, and reports pointer or parity faults on err_o; NEVER_CLEARS documents that clr_i stays low. DEPTH 0 is a combinational pass-through and requires PASS. DEPTH 1 uses a single register whose full flag SECURE duplicates inverted. Deeper FIFOs hold wready_o and rvalid_o low for the first cycle after reset.

Evaluate prim_fifo_assert.svh whenever this file is included, even when the FIFO assertions are otherwise unused, so including the FIFO still pulls in that assert header.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`WIDTH`	`int unsigned`	`16`	Datapath width.
`PASS`	`bit`	`1'b1`	1 allows a write to pass through an empty FIFO in the same cycle.
`DEPTH`	`int unsigned`	`4`	Storage depth.
`OUTPUT_ZERO_IF_EMPTY`	`bit`	`1'b1`	1 forces rdata_o to 0 when the FIFO is empty.
`NEVER_CLEARS`	`bit`	`1'b0`	Declares that clr_i stays low; checked by assertion, and with SECURE it drops the clear from the pointers.
`SECURE`	`bit`	`1'b0`	Uses prim_count for pointers and adds per-entry parity.
`DepthW`	`int`	`prim_util_pkg::vbits(DEPTH+1)`	Width of depth_o; derived.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input		FIFO clock.
`rst_ni`	input		Async reset, active-low.
`clr_i`	input		Synchronous clear / flush.
`wvalid_i`	input		Write valid.
`wready_o`	output		Write ready.
`wdata_i`	input	`[WIDTH-1:0]`	Write data.
`rvalid_o`	output		Read valid.
`rready_i`	input		Read ready.
`rdata_o`	output	`[WIDTH-1:0]`	Read data.
`full_o`	output		FIFO full.
`depth_o`	output	`[DepthW-1:0]`	Current occupancy.
`err_o`	output		Pointer or parity integrity fault; always 0 unless SECURE.