prim_prog_clk_div_posedge

Divide clk_i on the positive edge with a programmable ratio and duty cycle.

update_settings_i samples divider_i and duty_cycle_i into the divider; after reset the divider is INITIAL_DIVIDER_VAL with a 50% duty cycle. use_clk_div_i selects the divided clock through a glitch-free mux; otherwise clk_o follows clk_i. test_en_i muxes scan_rst_ni onto the reset path; it does not bypass the divider. RESET_WIDTH stretches the synchronized reset in clk_i cycles.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`RESET_WIDTH`	`int unsigned`	`16`	Synchronized reset stretch in clk_i cycles.
`INITIAL_DIVIDER_VAL`	`bit [7:0]`	`8'd2`	Divider value after reset.
`DIVIDED_CLOCK_ON_RESET`	`bit`	`1'b0`	Starts with the divider engaged after reset.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	Source clock.
`rst_ni`	input	`logic`	Async reset, active-low; synchronized to clk_i internally.
`update_settings_i`	input	`logic`	Samples divider_i and duty_cycle_i.
`divider_i`	input	`logic [7:0]`	Divide ratio in clk_i cycles; values below 2 act as 2.
`duty_cycle_i`	input	`logic [7:0]`	High time in 1/256 of the divided period, clamped to 1 to divider-1 clk_i cycles; 0 acts as 1.
`use_clk_div_i`	input	`logic`	Selects the divided clock when high.
`test_en_i`	input	`logic`	Test mode; selects scan_rst_ni as the internal reset.
`scan_rst_ni`	input	`logic`	DFT scan reset, active-low.
`clk_o`	output	`logic`	Divided or bypassed clock.