prim_pulse_signal

Shape pulse_in_i with programmable pre- and post-wait counts.

pulse_start_i samples pulse_in_i and starts a sequence: drive the sampled level for pre_pulse_wait_i + 1 cycles, assert pulse_out_o for post_pulse_wait_i + 1 cycles, then return to idle. A new pulse_start_i during the sequence reloads the count of the current phase. IS_ACTIVE_HIGH sets the polarity of pulse_out_o. pulse_done_o is high while idle and low for the whole sequence; pulse_out_o sits at its asserted level while idle, so use it only while pulse_done_o is low.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`COUNT_WIDTH`	`int`	`16`	Width of the wait counters.
`IS_ACTIVE_HIGH`	`bit`	`0`	1 makes pulse_out_o active-high; 0 makes it active-low.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	Pulse clock.
`rst_ni`	input	`logic`	Active-low reset, sampled synchronously.
`pulse_start_i`	input	`logic`	Arms a shaped pulse sequence.
`pre_pulse_wait_i`	input	`logic [COUNT_WIDTH-1:0]`	Cycles, minus one, of the sampled pulse_in_i level before pulse_out_o asserts.
`post_pulse_wait_i`	input	`logic [COUNT_WIDTH-1:0]`	Cycles, minus one, that pulse_out_o stays asserted.
`pulse_in_i`	input	`logic`	Level sampled on pulse_start_i and driven during the pre-pulse wait.
`pulse_out_o`	output	`logic`	Shaped pulse output; valid while pulse_done_o is low.
`pulse_done_o`	output	`logic`	High while idle; low while a sequence runs.