prim_ram_1p_adv_ext

Wrap a single-port SRAM with optional ECC or parity, pipelines, and tiled external RAM ports.

INST_DEPTH smaller than DEPTH tiles into ceil(DEPTH/INST_DEPTH) external RAM instances, each INST_DEPTH deep.

ENABLE_ECC and ENABLE_PARITY select per-word ECC or per-byte parity. HAMMING_ECC switches from HSIAO to Hamming; HSIAO is more compact and faster. ECC supports WIDTH of 16 or 32 and whole-word writes only; parity is odd per byte and needs DATA_BITS_PER_MASK of 8.

Read data returns one cycle after the request; ENABLE_INPUT_PIPELINE and ENABLE_OUTPUT_PIPELINE each add one cycle of read latency.

alert_o rises on an invalid multi-bit (MuBi4) encoding of the internal request, write or read-valid controls. rerror_o bit1 is uncorrectable and bit0 is correctable; parity errors set bit1.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`DEPTH`	`int`	`512`	Logical memory depth.
`INST_DEPTH`	`int`	`DEPTH`	Per-tile depth; smaller than DEPTH tiles into ceil(DEPTH/INST_DEPTH) external RAM ports, each INST_DEPTH deep.
`WIDTH`	`int`	`32`	Data width.
`DATA_BITS_PER_MASK`	`int`	`1`	Data bits covered by each write-mask bit; only checked to be 8 when ENABLE_PARITY is set.
`MEM_INIT_FILE`		`""`	Declared but unused; the external RAM owns initialization.
`ENABLE_ECC`	`bit`	`0`	Enables per-word ECC.
`ENABLE_PARITY`	`bit`	`0`	Enables per-byte parity.
`ENABLE_INPUT_PIPELINE`	`bit`	`0`	Adds an input register; read latency +1.
`ENABLE_OUTPUT_PIPELINE`	`bit`	`0`	Adds an output register; read latency +1.
`HAMMING_ECC`	`bit`	`0`	Selects Hamming ECC instead of HSIAO; HSIAO is more compact and faster.
`Aw`	`int`	`prim_util_pkg::vbits(DEPTH)`	Logical address width.
`NumRamInst`	`int`	`prim_util_pkg::ceil_div(DEPTH, INST_DEPTH)`	Number of tiled RAM instances.
`InstAw`	`int`	`prim_util_pkg::vbits(INST_DEPTH)`	Per-instance address width.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input		Memory clock.
`rst_ni`	input		Async reset, active-low.
`req_i`	input		Access request.
`write_i`	input		Write when high, read when low.
`addr_i`	input	`[Aw-1:0]`	Logical word address.
`wdata_i`	input	`[WIDTH-1:0]`	Write data.
`wmask_i`	input	`[WIDTH-1:0]`	Per-bit write mask; must be all ones with ECC.
`rdata_o`	output	`logic [WIDTH-1:0]`	Read data.
`rvalid_o`	output	`logic`	Read response (rdata_o) is valid.
`rerror_o`	output	`logic [1:0]`	Bit1 uncorrectable, bit0 correctable; 0 unless rvalid_o.
`alert_o`	output	`logic`	Invalid MuBi4 encoding on an internal control signal.
`ram_req_o`	output	`ram_req_t [NumRamInst-1:0]`	Per-tile external RAM requests.
`ram_rsp_i`	input	`ram_rsp_t [NumRamInst-1:0]`	Per-tile external RAM responses.