prim_ram_1p_scr_ext

Scramble a single-port SRAM front-end over prim_ram_1p_adv_ext tiles.

Refuse to grant req_i while key_valid_i is low. intg_error_i suppresses any real memory transaction on an upstream integrity fault.

Delay writes one cycle so reads and writes share the PRINCE keystream unit. Hold a pending write across a following read and detect address collisions; a colliding read returns the masked bytes of the pending write data. Read data returns one cycle after the grant. The inner RAM runs without ECC, so rerror_o can only report parity errors.

Keep cipher rounds low for latency. PRINCE's original 5 half-rounds are 2*5+1 effective rounds; NUM_PRINCE_ROUNDS_HALF of 3 is about 7 effective rounds and must be in [1..5].

NUM_DIFF_ROUNDS of 0 disables diffusion because non-linear data diffusion can interact adversely with end-to-end ECC. Enable it only with full knowledge of that interaction, for example with byte parity.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`DEPTH`	`int`	`16*1024`	Logical depth; must be a power of 2 if NUM_ADDR_SCR_ROUNDS > 0.
`INST_DEPTH`	`int`	`DEPTH`	Per-tile depth for RAM tiling.
`WIDTH`	`int`	`32`	Data width; must be byte-aligned when byte parity is enabled.
`DATA_BITS_PER_MASK`	`int`	`8`	Must be 8 when byte parity is enabled.
`ENABLE_PARITY`	`bit`	`0`	Enables byte parity.
`NUM_PRINCE_ROUNDS_HALF`	`int`	`3`	PRINCE half-rounds in [1..5]; kept low for latency. Original PRINCE uses 5 half-rounds (2*5+1 effective); 3 is about 7 effective rounds.
`NUM_DIFF_ROUNDS`	`int`	`0`	Extra diffusion rounds; 0 disables diffusion. Default 0 because non-linear data diffusion can interact adversely with end-to-end ECC; enable only with full knowledge of that interaction (for example with byte parity).
`DIFF_WIDTH`	`int`	`DATA_BITS_PER_MASK`	Diffusion block width; at least 4, and 8 with parity. Use 8 for intra-byte diffusion.
`NUM_ADDR_SCR_ROUNDS`	`int`	`2`	Address scrambling rounds; 0 disables address scrambling.
`REPLICATE_KEY_STREAM`	`bit`	`1'b0`	1 replicates the same 64-bit keystream across a wider data port; 0 replicates the cipher with a wider nonce for a unique keystream across the full width.
`AddrWidth`	`int`	`prim_util_pkg::vbits(DEPTH)`	Logical address width; derived.
`NumParScr`	`int`	`(REPLICATE_KEY_STREAM) ? 1 : (WIDTH + 63) / 64`	Parallel PRINCE instances so the keystream covers WIDTH; PRINCE block size is 64 bits.
`NumParKeystr`	`int`	`(REPLICATE_KEY_STREAM) ? (WIDTH + 63) / 64 : 1`	Parallel keystream replicas when REPLICATE_KEY_STREAM is set.
`DataKeyWidth`	`int`	`128`	Scrambling key width from PRINCE; all parallel ciphers share the key with different IVs.
`NonceWidth`	`int`	`64 * NumParScr`	Nonce width; each 64-bit scrambling primitive needs a 64-bit IV.
`NumRamInst`	`int`	`prim_util_pkg::ceil_div(DEPTH, INST_DEPTH)`	Number of tiled RAM instances.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input		Memory clock.
`rst_ni`	input		Async reset, active-low.
`key_valid_i`	input		Scrambling key is live; requests are not granted while low.
`key_i`	input	`[DataKeyWidth-1:0]`	Scrambling key.
`nonce_i`	input	`[NonceWidth-1:0]`	Scrambling nonce; the top AddrWidth bits key address scrambling and the low bits form the keystream IVs.
`req_i`	input		Unscrambled access request.
`gnt_o`	output	`logic`	Request grant; req_i gated combinationally by key_valid_i.
`write_i`	input		Write when high, read when low.
`addr_i`	input	`[AddrWidth-1:0]`	Logical address before scramble.
`wdata_i`	input	`[WIDTH-1:0]`	Plaintext write data.
`wmask_i`	input	`[WIDTH-1:0]`	Write mask; must be byte-aligned for parity.
`intg_error_i`	input		Suppresses any real memory transaction on an integrity fault and kills the matching read response.
`rdata_o`	output	`logic [WIDTH-1:0]`	Descrambled read data; 0 while rvalid_o is low.
`rvalid_o`	output	`logic`	Read response (rdata_o) is valid.
`rerror_o`	output	`logic [1:0]`	Bit1 flags a parity error; bit0, correctable, is always 0.
`raddr_o`	output	`logic [AddrWidth-1:0]`	Unscrambled address of the last granted read, for error reporting.
`wr_collision_o`	output	`logic`	Read hits a pending write address; valid with rvalid_o.
`write_pending_o`	output	`logic`	High while a write is granted or a delayed write is being committed to memory.
`alert_o`	output	`logic`	Invalid MuBi4 encoding on an internal control signal, including those of the inner RAM.
`ram_req_o`	output	`ram_req_t [NumRamInst-1:0]`	Per-tile external RAM requests from the inner prim_ram_1p_adv_ext.
`ram_rsp_i`	input	`ram_rsp_t [NumRamInst-1:0]`	Per-tile external RAM responses.