prim_refclk_count_w_cdc

Count on refclk_i and synchronize the value into out_clk_i.

cnt_en_i enables counting; cnt_update_i, in the out_clk_i domain, sends cnt_update_value_i through a one-entry async FIFO and the counter loads it on refclk_i. An update that arrives while counting is disabled is discarded, and a second update written before the first has crossed is dropped. REF_COUNT_WIDTH defaults to 54, about five years at 100 MHz. prst_ni is the async reset for the reference domain; it is also synchronized into out_clk_i for the FIFO write side. Split the counter into parallel chunks for timing. count_o crosses into out_clk_i in Gray code through a three-flop synchronizer.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`REF_COUNT_WIDTH`	`int unsigned`	`54`	Reference counter width; ~5 years at 100 MHz when 54.

Ports

Table 2. Ports
Name	Direction	Type	Description
`refclk_i`	input	`logic`	Reference clock.
`prst_ni`	input	`logic`	Async reset in the reference domain, active-low.
`out_clk_i`	input	`logic`	Destination clock for the CDC'd count and clock of cnt_update_i.
`cnt_en_i`	input	`logic`	Enables counting on refclk_i; asynchronous, synchronized into refclk_i.
`cnt_update_i`	input	`logic`	Single-cycle update strobe in the out_clk_i domain.
`cnt_update_value_i`	input	`ref_count_t`	Value loaded when cnt_update_i is high; out_clk_i domain.
`count_o`	output	`ref_count_t`	Count synchronized into out_clk_i.