prim_sync3_pulse

Pulse dst_pulse_o once for each src_pulse_i across a clock-domain crossing.

Toggle a level on src_clk_i and edge-detect it on dst_clk_i after a 3-flop sync. src_rst_ni clears the source toggle state and, synchronized into dst_clk_i, the destination synchronizer. Each high cycle of src_pulse_i flips the toggle, so the input must be a single-cycle pulse. Two source pulses closer together than the destination can resolve cancel each other and produce no dst_pulse_o.

Ports

Table 1. Ports
Name	Direction	Type	Description
`src_clk_i`	input	`logic`	Source clock.
`src_pulse_i`	input	`logic`	Source-domain pulse to forward; high for one src_clk_i cycle.
`src_rst_ni`	input	`logic`	Active-low reset, sampled synchronously on src_clk_i and synchronized into dst_clk_i for the destination side.
`dst_clk_i`	input	`logic`	Destination clock.
`dst_pulse_o`	output	`logic`	One-cycle pulse on dst_clk_i.