prim_sync4r

Synchronize each bit of d_i into clk_i through a four-flop resettable chain.

Each bit uses its own prim_flop_4sync_r cell. Under SIMULATION, prim_cdc_rand_delay randomizes when a change on d_i reaches the first stage to model CDC uncertainty; synthesis connects d_i to the cells directly. rst_ni clears every stage to 0 asynchronously.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`WIDTH`	`int unsigned`	`1`	Number of independent bits synchronized.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	Destination clock.
`d_i`	input	`logic [WIDTH-1:0]`	Asynchronous bits, each resolved independently.
`rst_ni`	input	`logic`	Active-low asynchronous reset.
`q_o`	output	`logic [WIDTH-1:0]`	Synchronized bits in the clk_i domain.