prim_sync_data_autohs

Cross data_i from clk_src_i to clk_dst_i with an automatic req/ack toggle handshake.

Sample data_i in the source domain at the start of every handshake round, whether or not it changed, and capture the held sample in the destination when its request toggle arrives. DEPTH of 2 selects 2-flop synchronizers on the toggle wires; any other value selects 3-flop ones. Wait for the destination ack before sampling again, so changes of data_i shorter than one round trip can be missed.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`WIDTH`	`int unsigned`	`1`	Datapath width.
`DEPTH`	`int unsigned`	`2`	Sync depth on handshake toggles; 2 gives two flops, any other value three.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_src_i`	input	`logic`	Source clock.
`rst_src_ni`	input	`logic`	Active-low reset for the source domain; the source registers sample it synchronously.
`data_i`	input	`logic [WIDTH-1:0]`	Source-domain data.
`clk_dst_i`	input	`logic`	Destination clock.
`rst_dst_ni`	input	`logic`	Active-low reset for the destination domain; the destination registers sample it synchronously.
`data_o`	output	`logic [WIDTH-1:0]`	Destination-domain captured data; 0 after reset.