prim_sync_reset

Stretch and synchronize an async active-low reset into clk_i.

sync_rst_no asserts asynchronously with rst_ni and deasserts after WIDTH clk_i cycles of rst_ni deasserted. The first min(WIDTH, 4) stages are a prim_flop_*sync cell; each stage beyond 4 is a prim_metastab_hardened_dffr. test_mode_i, active-high, swaps scan_rst_ni onto the hazard-free bypass mux. sync_rst_no is the synchronized active-low reset output.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`WIDTH`	`int unsigned`	`16`	Synchronizer stages, at least 2; clk_i cycles from rst_ni deasserting to sync_rst_no deasserting.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	Destination clock.
`rst_ni`	input	`logic`	Async reset to synchronize, active-low.
`test_mode_i`	input	`logic`	Test mode, active-high; selects scan_rst_ni.
`scan_rst_ni`	input	`logic`	Scan reset used in test mode, active-low.
`sync_rst_no`	output	`logic`	Synchronized reset output, active-low.