prim_updown_counter

Count up or down with saturation, clear, set, and commit.

RESET_VALUE can be nonzero so a down-counter need not start at 0. incr_en_i and decr_en_i together do not count; either alone steps by step_i. clear_i takes priority over set_i, which takes priority over counting. commit_i freezes cnt_after_commit_o into count_o; without it the next value stays speculative, so clear_i and set_i also take effect only with commit_i.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`WIDTH`	`int`	`16`	Counter width.
`RESET_VALUE`	`logic [WIDTH-1:0]`	`'0`	Value loaded on reset or clear_i; may be nonzero when the counter is used as a down-counter.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input		Counter clock.
`rst_ni`	input		Active-low reset, sampled synchronously; loads RESET_VALUE.
`clear_i`	input		Loads RESET_VALUE when committed.
`set_i`	input		Loads set_cnt_i when committed.
`set_cnt_i`	input	`ctr_t`	Value loaded when set_i is high.
`incr_en_i`	input		Counts up by step_i.
`decr_en_i`	input		Counts down by step_i.
`step_i`	input	`ctr_t`	Increment or decrement step when enabled.
`commit_i`	input		Commits the pending next value.
`count_o`	output	`ctr_t`	Current committed counter state.
`cnt_after_commit_o`	output	`ctr_t`	Next counter state if commit_i is taken.
`err_o`	output	`logic`	Hardening error output; tied to 0.