tlul_adapter_host

Convert a host req/gnt/rvalid bus into TL-UL.

Requests and responses pass combinationally. When MAX_REQS > 1 a counter assigns a_source IDs 0 to MAX_REQS-1 in rotation; when MAX_REQS == 1 a_source is always 0. The host must not have more requests in flight than MAX_REQS. d_ready is tied high, so the host must accept every response in the cycle it arrives.

The adapter does not reorder responses when MAX_REQS > 1. The host must either target an address space that returns in order or not depend on order.

The outgoing address is always word aligned and the access size is always the TL word size (TL_DW). The A-channel opcode and mask follow the access:

Full-lane writes use PUT_FULL_DATA.
Other writes use PUT_PARTIAL_DATA, with the mask generated from be_i.
Reads enable every lane in the mask as required by TL-UL.

Integrity handling is optional:

When ENABLE_DATA_INTG_GEN is set, compute data integrity on host write data; otherwise send wdata_intg_i.
Response integrity is always checked. When ENABLE_RSP_DATA_INTG_CHECK is set, also check integrity on returned read data.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`MAX_REQS`	`int unsigned`	`2`	Maximum outstanding host requests.
`ENABLE_DATA_INTG_GEN`	`bit`	`0`	Compute data integrity on write data.
`ENABLE_RSP_DATA_INTG_CHECK`	`bit`	`0`	Check integrity on returned read data.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input		System clock.
`rst_ni`	input		Active-low reset.
`req_i`	input		Host request valid.
`gnt_o`	output	`logic`	Host request grant.
`addr_i`	input	`logic [top_pkg::TL_AW-1:0]`	Host byte address; word-aligned on tl_o.
`we_i`	input	`logic`	Host write enable.
`wdata_i`	input	`logic [top_pkg::TL_DW-1:0]`	Host write data.
`wdata_intg_i`	input	`logic [DATA_INTG_WIDTH-1:0]`	Integrity bits sent with wdata_i when ENABLE_DATA_INTG_GEN is clear.
`be_i`	input	`logic [top_pkg::TL_DBW-1:0]`	Host byte enables; form the TL-UL mask.
`instr_type_i`	input	`mubi4_t`	MuBi4 instruction-type user bit.
`user_rsvd_i`	input	`logic [RSVD_WIDTH-1:0]`	Reserved A-channel user bits.
`valid_o`	output	`logic`	Host response valid.
`rdata_o`	output	`logic [top_pkg::TL_DW-1:0]`	Host read data.
`rdata_intg_o`	output	`logic [DATA_INTG_WIDTH-1:0]`	Integrity bits with rdata_o.
`err_o`	output	`logic`	d_error or an integrity failure on this response.
`intg_err_o`	output	`logic`	Integrity failure; sticky until reset.
`tl_o`	output	`tl_h2d_t`	TL-UL host-to-device toward the fabric.
`tl_i`	input	`tl_d2h_t`	TL-UL device-to-host from the fabric.