tlul_adapter_reg

Adapt TL-UL device traffic onto a register read/write interface.

Act as a TL-UL device. Accept GET, PUT_PARTIAL_DATA, and PUT_FULL_DATA on the A channel and pass each read or write to the register interface in the same cycle. Return the register response on the D channel in the next cycle, whatever ACCESS_LATENCY is. One request is outstanding at a time: A_READY stays low until the response is accepted.

Forward a request only when every check passes:

A_OPCODE is GET, PUT_PARTIAL_DATA, or PUT_FULL_DATA.
A_SIZE is 0, 1, or 2 (a 1-, 2-, or 4-byte operation).
A_ADDRESS is naturally aligned for the A_SIZE byte width, and word aligned for writes.
A_MASK is true only for active byte lanes. The first active lane is the address modulo the TL-UL data-bus width.
A_USER.INSTR_TYPE is a valid MuBi4 encoding.
A_OPCODE is GET when A_USER.INSTR_TYPE is MuBi4True.
A_USER.INSTR_TYPE is not MuBi4True, or en_ifetch_i is MuBi4True.
The command and A-channel data integrity checks pass, when CMD_INTG_CHECK is set.

A request that fails a check reaches no register and gets D_ERROR on the response. D_DATA is all ones for writes and errored requests.

Besides the generated reg_top modules, this adapter serves modules with special needs, such as the vendored prim_reg_cdc and spi_host_window, which is why its parameter set is broader than reg_top needs.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`CMD_INTG_CHECK`	`bit`	`0`	Check A-channel command integrity with tlul_cmd_intg_chk. On a mismatch, re_o and we_o stay low, D_ERROR is set, and intg_error_o rises the next cycle.
`ENABLE_RSP_INTG_GEN`	`bit`	`0`	Generate D_USER.RSP_INTG; zero when clear.
`ENABLE_DATA_INTG_GEN`	`bit`	`0`	Generate D_USER.DATA_INTG; zero when clear.
`REG_AW`	`int`	`8`	Register address width. Higher A_ADDRESS bits are ignored.
`REG_DW`	`int`	`32`	Register data width. Must match the TL-UL data width (MatchedWidth_A).
`ACCESS_LATENCY`	`int`	`0`	0 or 1. 0: the register response is combinatorial and is flopped here. 1: the response arrives the cycle after re_o/we_o and is forwarded combinatorially.
`RegBw`	`int`	`REG_DW/8`	Register byte-enable width from REG_DW.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input		System clock.
`rst_ni`	input		Active-low reset.
`tl_i`	input	`tl_h2d_t`	TL-UL host-to-device request.
`tl_o`	output	`tl_d2h_t`	TL-UL device-to-host response.
`en_ifetch_i`	input	`mubi4_t`	MuBi4True allows Gets whose A_USER.INSTR_TYPE is MuBi4True (processor fetches).
`intg_error_o`	output	`logic`	Integrity error, sticky until reset. Only rises when CMD_INTG_CHECK is set.
`re_o`	output	`logic`	Register read enable.
`we_o`	output	`logic`	Register write enable.
`addr_o`	output	`logic [REG_AW-1:0]`	A_ADDRESS[REG_AW-1:0], bits 1:0 cleared; 0 if REG_AW <= 2.
`wdata_o`	output	`logic [REG_DW-1:0]`	Register write data.
`be_o`	output	`logic [RegBw-1:0]`	Register byte enables from the TL-UL mask.
`busy_i`	input		Stall: A_READY drops and no new operation is accepted.
`rdata_i`	input	`[REG_DW-1:0]`	Register read data, ACCESS_LATENCY cycles after re_o.
`error_i`	input		Register read or write error, ACCESS_LATENCY cycles after re_o/we_o. Sets D_ERROR and forces D_DATA to '1.